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2019-09-17riscv: Add a helper routine for finding firmwareBin Meng
This adds a helper routine for finding firmware. It is currently used only for "-bios default" case. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: plic: Remove unused interrupt functionsAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Jonathan Behrens <fintelia@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: sifive_u: Fix clock-names property for ethernet nodeGuenter Roeck
The correct property name is clock-names, not clocks-names. Without this patch, the Ethernet driver fails to instantiate with the following error. macb 100900fc.ethernet: failed to get macb_clk (-2) macb: probe of 100900fc.ethernet failed with error -2 Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: sivive_u: Add dummy serial clock and aliases entry for uartGuenter Roeck
The riscv uart needs valid clocks. This requires a refereence to the clock node. Since the SOC clock is not emulated by qemu, add a reference to a fixed clock instead. The clock-frequency entry in the uart node does not seem to be necessary, so drop it. In addition to a reference to the clock, the driver also needs an aliases entry for the serial node. Add it as well. Without this patch, the serial driver fails to instantiate with the following error message. sifive-serial 10013000.uart: unable to find controller clock sifive-serial: probe of 10013000.uart failed with error -2 when trying to boot Linux. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: sifive_u: Add support for loading initrdGuenter Roeck
Add support for loading initrd with "-initrd <filename>" to the sifive_u machine. This lets us boot into Linux without disk drive. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
virtio,vhost,pc: features, fixes, cleanups. Virtio 1.0 support for virtio-mmio. Misc fixes, cleanups. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Mon 16 Sep 2019 16:17:30 BST # gpg: using RSA key 281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: virtio-mmio: implement modern (v2) personality (virtio-1) virtio pmem: user document intel_iommu: Remove the caching-mode check during flag change pc/q35: Disallow vfio-pci hotplug without VT-d caching mode qdev/machine: Introduce hotplug_allowed hook intel_iommu: Sanity check vfio-pci config on machine init done backends/vhost-user.c: prevent using uninitialized vqs vhost-user-blk: prevent using uninitialized vqs docs/nvdimm: add example on persistent backend setup MAINTAINERS: update virtio-rng and virtio-serial maintainer Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-17Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* Fix Patchew CI failures (myself) * i386 fw_cfg refactoring (Philippe) * pmem bugfix (Stefan) * Support for accessing cstate MSRs (Wanpeng) * exec.c cleanups (Wei Yang) * Improved throttling (Yury) * elf-ops.h coverity fix (Stefano) # gpg: Signature made Mon 16 Sep 2019 16:13:12 BST # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (29 commits) hw/i386/pc: Extract the x86 generic fw_cfg code hw/i386/pc: Rename pc_build_feature_control() as generic fw_cfg_build_* hw/i386/pc: Let pc_build_feature_control() take a MachineState argument hw/i386/pc: Let pc_build_feature_control() take a FWCfgState argument hw/i386/pc: Rename pc_build_smbios() as generic fw_cfg_build_smbios() hw/i386/pc: Let pc_build_smbios() take a generic MachineState argument hw/i386/pc: Let pc_build_smbios() take a FWCfgState argument hw/i386/pc: Replace PCMachineState argument with MachineState in fw_cfg_arch_create hw/i386/pc: Pass the CPUArchIdList array by argument hw/i386/pc: Pass the apic_id_limit value by argument hw/i386/pc: Pass the boot_cpus value by argument hw/i386/pc: Rename bochs_bios_init as more generic fw_cfg_arch_create hw/i386/pc: Use address_space_memory in place hw/i386/pc: Extract e820 memory layout code hw/i386/pc: Use e820_get_num_entries() to access e820_entries cpus: Fix throttling during vm_stop qemu-thread: Add qemu_cond_timedwait memory: inline and optimize devend_memop memory: fetch pmem size in get_file_size() elf-ops.h: fix int overflow in load_elf() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-16virtio-mmio: implement modern (v2) personality (virtio-1)Sergio Lopez
Implement the modern (v2) personality, according to the VirtIO 1.0 specification. Support for v2 among guests is not as widespread as it'd be desirable. While the Linux driver has had it for a while, support is missing, at least, from Tianocore EDK II, NetBSD and FreeBSD. For this reason, the v2 personality is disabled, keeping the legacy behavior as default. Machine types willing to use v2, can enable it using MachineClass's compat_props. Signed-off-by: Sergio Lopez <slp@redhat.com> Message-Id: <20190913120559.40835-1-slp@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2019-09-16hw/i386/pc: Extract the x86 generic fw_cfg codePhilippe Mathieu-Daudé
Extract all the functions that are not PC-machine specific into the (arch-specific) fw_cfg.c file. This will allow other X86-machine to reuse these functions. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-16-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-09-16hw/i386/pc: Rename pc_build_feature_control() as generic fw_cfg_build_*Philippe Mathieu-Daudé
Now that the pc_build_feature_control_file() function has been refactored to not depend of PC specific types, rename it to a more generic name. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-15-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-09-16hw/i386/pc: Let pc_build_feature_control() take a MachineState argumentPhilippe Mathieu-Daudé
Let the pc_build_feature_control_file() function take a generic MachineState argument. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-14-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-09-16hw/i386/pc: Let pc_build_feature_control() take a FWCfgState argumentPhilippe Mathieu-Daudé
Pass the FWCfgState object by argument, this will allow us to remove the PCMachineState argument later. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-13-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-09-16hw/i386/pc: Rename pc_build_smbios() as generic fw_cfg_build_smbios()Philippe Mathieu-Daudé
Now that the pc_build_smbios() function has been refactored to not depend of PC specific types, rename it to a more generic name. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-12-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-09-16hw/i386/pc: Let pc_build_smbios() take a generic MachineState argumentPhilippe Mathieu-Daudé
Let the pc_build_smbios() function take a generic MachineState argument. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-11-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-09-16hw/i386/pc: Let pc_build_smbios() take a FWCfgState argumentPhilippe Mathieu-Daudé
Pass the FWCfgState object by argument, this will allow us to remove the PCMachineState argument later. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-10-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-09-16hw/i386/pc: Replace PCMachineState argument with MachineState in ↵Paolo Bonzini
fw_cfg_arch_create In the previous commit we removed the last access to PCMachineState. Replace it with a generic MachineState argument and use it to retrieve the CPUArchIdList. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-09-16hw/i386/pc: Pass the CPUArchIdList array by argumentPhilippe Mathieu-Daudé
Pass the CPUArchIdList array by argument, this will allow us to remove the PCMachineState argument later. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-8-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-09-16hw/i386/pc: Pass the apic_id_limit value by argumentPhilippe Mathieu-Daudé
Pass the apic_id_limit value by argument, this will allow us to remove the PCMachineState argument later. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-7-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-09-16hw/i386/pc: Pass the boot_cpus value by argumentPhilippe Mathieu-Daudé
The boot_cpus is used once. Pass it by argument, this will allow us to remove the PCMachineState argument later. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-6-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-09-16hw/i386/pc: Rename bochs_bios_init as more generic fw_cfg_arch_createPhilippe Mathieu-Daudé
The bochs_bios_init() function is not restricted to the Bochs BIOS and is useful to other BIOS. Since it is not specific to the PC machine, and can be reused by other machines of the X86 architecture, rename it as fw_cfg_arch_create(). Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-5-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-09-16hw/i386/pc: Use address_space_memory in placePhilippe Mathieu-Daudé
The address_space_memory variable is used once. Use it in place and remove the argument. Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-4-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-09-16hw/i386/pc: Extract e820 memory layout codePhilippe Mathieu-Daudé
Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-3-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-09-16hw/i386/pc: Use e820_get_num_entries() to access e820_entriesPhilippe Mathieu-Daudé
To be able to extract the e820* code out of this file (in the next patch), access e820_entries with its correct helper. Reviewed-by: Li Qiang <liq3ea@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190818225414.22590-2-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-09-16intel_iommu: Remove the caching-mode check during flag changePeter Xu
That's never a good place to stop QEMU process... Since now we have both the machine done sanity check and also the hotplug handler, we can safely remove this to avoid that. Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20190916080718.3299-5-peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2019-09-16pc/q35: Disallow vfio-pci hotplug without VT-d caching modePeter Xu
Instead of bailing out when trying to hotplug a vfio-pci device with below configuration: -device intel-iommu,caching-mode=off With this we can return a warning message to the user via QMP/HMP and the VM will continue to work after failing the hotplug: (qemu) device_add vfio-pci,bus=root.3,host=05:00.0,id=vfio1 Error: Device assignment is not allowed without enabling caching-mode=on for Intel IOMMU. Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20190916080718.3299-4-peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2019-09-16qdev/machine: Introduce hotplug_allowed hookPeter Xu
Introduce this new per-machine hook to give any machine class a chance to do a sanity check on the to-be-hotplugged device as a sanity test. This will be used for x86 to try to detect some illegal configuration of devices, e.g., possible conflictions between vfio-pci and x86 vIOMMU. Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20190916080718.3299-3-peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2019-09-16intel_iommu: Sanity check vfio-pci config on machine init donePeter Xu
This check was previously only happened when the IOMMU is enabled in the guest. It was always too late because the enabling of IOMMU normally only happens during the boot of guest OS. It means that we can bail out and exit directly during the guest OS boots if the configuration of devices are not supported. Or, if the guest didn't enable vIOMMU at all, then the user can use the guest normally but as long as it reconfigure the guest OS to enable the vIOMMU then reboot, the user will see the panic right after the reset when the next boot starts. Let's make this failure even earlier so that we force the user to use caching-mode for vfio-pci devices when with the vIOMMU. So the user won't get surprise at least during execution of the guest, which seems a bit nicer. This will affect some user who didn't enable vIOMMU in the guest OS but was using vfio-pci and the vtd device in the past. However I hope it's not a majority because not enabling vIOMMU with the device attached is actually meaningless. We still keep the old assertion for safety so far because the hotplug path could still reach it, so far. Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20190916080718.3299-2-peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2019-09-16elf-ops.h: fix int overflow in load_elf()Stefano Garzarella
This patch fixes a possible integer overflow when we calculate the total size of ELF segments loaded. Reported-by: Coverity (CID 1405299) Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Stefano Garzarella <sgarzare@redhat.com> Message-Id: <20190910124828.39794-1-sgarzare@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-09-16hw/i386: Move CONFIG_ACPI_PCI to CONFIG_PCCole Robinson
CONFIG_ACPI_PCI is a hard requirement of acpi-build.c, which is built unconditionally for x86 target. Putting it in default-configs/ suggests that it can be easily disabled, which isn't true. Relocate the symbol with the other acpi-build.c requirements, under 'config PC'. This is similar to what is done for the arm 'virt' machine type and CONFIG_ACPI_PCI Signed-off-by: Cole Robinson <crobinso@redhat.com> Message-Id: <e73e6edff68fd30d69c6a1d02c9ef9192f773c63.1568049871.git.crobinso@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-09-16vhost-user-blk: prevent using uninitialized vqsRaphael Norwitz
Same rational as: e6cc11d64fc998c11a4dfcde8fda3fc33a74d844 Of the 3 virtqueues, seabios only sets cmd, leaving ctrl and event without a physical address. This can cause vhost_verify_ring_part_mapping to return ENOMEM, causing the following logs: qemu-system-x86_64: Unable to map available ring for ring 0 qemu-system-x86_64: Verify ring failure on region 0 This has already been fixed for vhost scsi devices and was recently vhost-user scsi devices. This commit fixes it for vhost-user-blk devices. Suggested-by: Phillippe Mathieu-Daude <philmd@redhat.com> Signed-off-by: Raphael Norwitz <raphael.norwitz@nutanix.com> Message-Id: <1566498865-55506-1-git-send-email-raphael.norwitz@nutanix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
2019-09-16Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20190913' into staging target-arm queue: * aspeed: add a GPIO controller to the SoC * aspeed: Various refactorings * aspeed: Improve DMA controller modelling * atomic_template: fix indentation in GEN_ATOMIC_HELPER * qemu-ga: Convert invocation documentation to rST # gpg: Signature made Fri 13 Sep 2019 16:49:05 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190913: qemu-ga: Convert invocation documentation to rST atomic_template: fix indentation in GEN_ATOMIC_HELPER aspeed/scu: Introduce a aspeed_scu_get_apb_freq() routine aspeed/scu: Introduce per-SoC SCU types aspeed/smc: Calculate checksum on normal DMA aspeed/smc: Inject errors in DMA checksum aspeed/smc: Add DMA calibration settings aspeed/smc: Add support for DMAs aspeed: Use consistent typenames aspeed: Remove unused SoC definitions aspeed: add a GPIO controller to the SoC hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-13aspeed/scu: Introduce a aspeed_scu_get_apb_freq() routineCédric Le Goater
The APB frequency can be calculated directly when needed from the HPLL_PARAM and CLK_SEL register values. This removes useless state in the model. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190904070506.1052-11-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-13aspeed/scu: Introduce per-SoC SCU typesCédric Le Goater
and use a class AspeedSCUClass to define each SoC characteristics. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190904070506.1052-10-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-13aspeed/smc: Calculate checksum on normal DMAChristian Svensson
This patch adds the missing checksum calculation on normal DMA transfer. According to the datasheet this is how the SMC should behave. Verified on AST1250 that the hardware matches the behaviour. Signed-off-by: Christian Svensson <bluecmd@google.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190904070506.1052-9-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-13aspeed/smc: Inject errors in DMA checksumCédric Le Goater
Emulate read errors in the DMA Checksum Register for high frequencies and optimistic settings of the Read Timing Compensation Register. This will help in tuning the SPI timing calibration algorithm. Errors are only injected when the property "inject_failure" is set to true as suggested by Philippe. The values below are those to expect from the first flash device of the FMC controller of a palmetto-bmc machine. Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190904070506.1052-8-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-13aspeed/smc: Add DMA calibration settingsCédric Le Goater
When doing calibration, the SPI clock rate in the CE0 Control Register and the read delay cycles in the Read Timing Compensation Register are set using bit[11:4] of the DMA Control Register. Signed-off-by: Cédric Le Goater <clg@kaod.org> Acked-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190904070506.1052-7-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-13aspeed/smc: Add support for DMAsCédric Le Goater
The FMC controller on the Aspeed SoCs support DMA to access the flash modules. It can operate in a normal mode, to copy to or from the flash module mapping window, or in a checksum calculation mode, to evaluate the best clock settings for reads. The model introduces two custom address spaces for DMAs: one for the AHB window of the FMC flash devices and one for the DRAM. The latter is populated using a "dram" link set from the machine with the RAM container region. Signed-off-by: Cédric Le Goater <clg@kaod.org> Acked-by: Joel Stanley <joel@jms.id.au> Message-id: 20190904070506.1052-6-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-13aspeed: Use consistent typenamesCédric Le Goater
Improve the naming of the different controller models to ease their generation when initializing the SoC. The rename of the SMC types is breaking migration compatibility. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190904070506.1052-5-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-13aspeed: Remove unused SoC definitionsCédric Le Goater
There are no QEMU Aspeed machines using the SoCs "ast2400-a0" or "ast2400". Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190904070506.1052-4-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-13aspeed: add a GPIO controller to the SoCRashmica Gupta
Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190904070506.1052-3-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-13hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500Rashmica Gupta
GPIO pins are arranged in groups of 8 pins labeled A,B,..,Y,Z,AA,AB,AC. (Note that the ast2400 controller only goes up to group AB). A set has four groups (except set AC which only has one) and is referred to by the groups it is composed of (eg ABCD,EFGH,...,YZAAAB). Each set is accessed and controlled by a bank of 14 registers. These registers operate on a per pin level where each bit in the register corresponds to a pin, except for the command source registers. The command source registers operate on a per group level where bits 24, 16, 8 and 0 correspond to each group in the set. eg. registers for set ABCD: |D7...D0|C7...C0|B7...B0|A7...A0| <- GPIOs |31...24|23...16|15....8|7.....0| <- bit position Note that there are a couple of groups that only have 4 pins. There are two ways that this model deviates from the behaviour of the actual controller: (1) The only control source driving the GPIO pins in the model is the ARM model (as there currently aren't models for the LPC or Coprocessor). (2) None of the registers in the model are reset tolerant (needs integration with the watchdog). Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com> Tested-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190904070506.1052-2-clg@kaod.org [clg: fixed missing header files made use of HWADDR_PRIx to fix compilation on windows ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-13Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-sep-12-2019' ↵Peter Maydell
into staging MIPS queue for September 12th, 2019 # gpg: Signature made Thu 12 Sep 2019 17:26:10 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-sep-12-2019: target/mips: gdbstub: Revert commit 8e0b373 hw/mips/mips_jazz: Remove no-longer-necessary override of do_unassigned_access target/mips: Switch to do_transaction_failed() hook hw/mips/mips_jazz: Override do_transaction_failed hook Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-13Merge remote-tracking branch ↵Peter Maydell
'remotes/dgilbert/tags/pull-migration-20190912a' into staging Migration pull 2019-09-12 New feature: UUID validation check from Yury Kotov plus a bunch of fixes. # gpg: Signature made Thu 12 Sep 2019 14:48:28 BST # gpg: using RSA key 45F5C71B4A0CB7FB977A9FA90516331EBC5BFDE7 # gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" [full] # Primary key fingerprint: 45F5 C71B 4A0C B7FB 977A 9FA9 0516 331E BC5B FDE7 * remotes/dgilbert/tags/pull-migration-20190912a: migration: fix one typo in comment of function migration_total_bytes() migration/qemu-file: fix potential buf waste for extra buf_index adjustment migration/qemu-file: remove check on writev_buffer in qemu_put_compression_data migration: Fix postcopy bw for recovery tests/migration: Add a test for validate-uuid capability tests/libqtest: Allow setting expected exit status migration: Add validate-uuid capability qemu-file: Rework old qemu_fflush comment migration: register_savevm_live doesn't need dev hw/net/vmxnet3: Fix leftover unregister_savevm migration: cleanup check on ops in savevm.handlers iterations migration: multifd_send_thread always post p->sem_sync when error happen Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-13Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell
staging Pull request # gpg: Signature made Wed 11 Sep 2019 15:36:02 BST # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: virtio-blk: Cancel the pending BH when the dataplane is reset Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-12hw/mips/mips_jazz: Remove no-longer-necessary override of do_unassigned_accessPeter Maydell
Now that the MIPS CPU implementation uses the new do_transaction_failed hook, we can remove the old code that handled the do_unassigned_access hook. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Hervé Poussineau <hpoussin@reactos.org> Message-Id: <20190802160458.25681-4-peter.maydell@linaro.org>
2019-09-12hw/mips/mips_jazz: Override do_transaction_failed hookPeter Maydell
The MIPS Jazz ('magnum' and 'pica61') boards have some code which overrides the CPU's do_unassigned_access hook, so they can intercept it and not raise exceptions on data accesses to invalid addresses, only for instruction fetches. We want to switch MIPS over to using the do_transaction_failed hook instead, so add an intercept for that as well, and make the board code install whichever hook the CPU is actually using. Once we've changed the CPU implementation we can remove the redundant code for the old hook. Note: I am suspicious that the behaviour as implemented here may not be what the hardware really does. It was added in commit 54e755588cf1e90f0b14 to restore the behaviour that was broken by commit c658b94f6e8c206c59d. But prior to commit c658b94f6e8c206c59d every MIPS board generated exceptions for instruction access to invalid addresses but not for data accesses; and other boards, notably Malta, were fixed by making all invalid accesses behave as reads-as-zero (see the call to empty_slot_init() in mips_malta_init()). Hardware that raises exceptions for instruction access and not data access seems to me to be an unlikely design, and it's possible that the right way to emulate this is to make the Jazz boards do what we did with Malta (or some variation of that). Nonetheless, since I don't have access to real hardware to test against I have taken the approach of "make QEMU continue to behave the same way it did before this commit". I have updated the comment to correct the parts that are no longer accurate and note that the hardware might behave differently. The test case for the need for the hook-hijacking is in https://bugs.launchpad.net/qemu/+bug/1245924 That BIOS will boot OK either with this overriding of both hooks, or with a simple "global memory region to ignore bad accesses of all types", so it doesn't provide evidence either way, unfortunately. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Hervé Poussineau <hpoussin@reactos.org> Message-Id: <20190802160458.25681-2-peter.maydell@linaro.org>
2019-09-12migration: register_savevm_live doesn't need devDr. David Alan Gilbert
Commit 78dd48df3 removed the last caller of register_savevm_live for an instantiable device (rather than a single system wide device); so trim out the parameter. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20190822115433.12070-1-dgilbert@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2019-09-12hw/net/vmxnet3: Fix leftover unregister_savevmDr. David Alan Gilbert
Commit 78dd48df3 reworked vmxnet3's live migration but left a straggling unregister_savevm call. Remove it, although it doesn't seem to have any bad effect. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20190822111218.12079-1-dgilbert@redhat.com> Reviewed-by: Dmitry Fleytman <dmitry.fleytman@gmail.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2019-09-10hw/misc: Mark most objects as "common" code to speed up compilation a litte bitThomas Huth
Most of the code in hw/misc/ does not directly depend on CPU-specific code. Mark it as "common" so that the code can be shared between e.g. qemu-system-arm and qemu-system-aarch64, or between the various mips flavours, instead of recompiling it for each and every target again and again. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20190902162638.28142-1-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-09-07m68k: Add serial controller to the NeXTcube machineThomas Huth
The NeXTcube uses a normal 8530 serial controller, so we can simply use our normal "escc" device here. While we're at it, also add a boot-serial-test for the next-cube machine, now that the serial output works. Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190831074519.32613-6-huth@tuxfamily.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
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