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2019-02-18Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.0-20190219' ↵Peter Maydell
into staging ppc patch queue 2019-02-19 Here's the next batch of ppc and spapr patches. Higlights are: * A bunch of improvements to TCG handling of vector instructions from Richard Henderson and Marc Cave-Ayland * Cleanup to the XICS interrupt controller from Greg Kurz, removing the special KVM subclasses which were a bad idea * Some refinements to the XIVE interrupt controller from Cédric Le Goater * Fix from Fabiano Rosas for a really dumb buffer overflow in the device tree code for memory hotplug * Code for allowing access to SPRs from the gdb stub from Fabiano Rosas * Assorted minor fixes and cleanups # gpg: Signature made Mon 18 Feb 2019 13:47:54 GMT # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-4.0-20190219: (43 commits) target/ppc: convert vmin* and vmax* to vector operations target/ppc: convert vadd*s and vsub*s to vector operations target/ppc: Split out VSCR_SAT to a vector field target/ppc: Add set_vscr_sat target/ppc: Use mtvscr/mfvscr for vmstate target/ppc: Add helper_mfvscr target/ppc: Remove vscr_nj and vscr_sat target/ppc: Use helper_mtvscr for reset and gdb target/ppc: Pass integer to helper_mtvscr target/ppc: convert xxsel to vector operations target/ppc: convert xxspltw to vector operations target/ppc: convert xxspltib to vector operations target/ppc: convert VSX logical operations to vector operations target/ppc: convert vsplt[bhw] to use vector operations target/ppc: convert vspltis[bhw] to use vector operations target/ppc: convert vaddu[b,h,w,d] and vsubu[b,h,w,d] over to use vector operations target/ppc: convert VMX logical instructions to use vector operations xics: Drop the KVM ICS class spapr/irq: Use the "simple" ICS class for KVM xics: Handle KVM interrupt presentation from "simple" ICS code ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-18Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2019-02-18' into ↵Peter Maydell
staging QAPI patches for 2019-02-18 # gpg: Signature made Mon 18 Feb 2019 13:44:30 GMT # gpg: using RSA key 3870B400EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-qapi-2019-02-18: qapi: move RTC_CHANGE to the target schema qmp: Deprecate query-events in favor of query-qmp-schema Revert "qapi-events: add 'if' condition to implicit event enum" qapi: remove qmp_unregister_command() qapi: make query-cpu-definitions depend on specific targets qapi: make query-cpu-model-expansion depend on s390 or x86 qapi: make query-gic-capabilities depend on TARGET_ARM target.json: add a note about query-cpu* not being s390x-specific qapi: make s390 commands depend on TARGET_S390X qapi: make rtc-reset-reinjection and SEV depend on TARGET_I386 qapi: New module target.json build: Deal with all of QAPI's .o in qapi/Makefile.objs build-sys: move qmp-introspect per target qapi: Generate QAPIEvent stuff into separate files qapi: Prepare for system modules other than 'builtin' qapi: Clean up modular built-in code generation a bit qapi: Fix up documentation for recent commit a95291007b2 qapi: Belatedly document modular code generation Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-18qapi: move RTC_CHANGE to the target schemaMarc-André Lureau
A few targets don't emit RTC_CHANGE, we could restrict the event to the tagets that do emit it. Note: There is a lot more of events & commands that we could restrict to capable targets, with the cost of some additional complexity, but the benefit of added correctness and better introspection. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190214152251.2073-19-armbru@redhat.com>
2019-02-18qapi: make s390 commands depend on TARGET_S390XMarc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190214152251.2073-11-armbru@redhat.com>
2019-02-18qapi: make rtc-reset-reinjection and SEV depend on TARGET_I386Marc-André Lureau
Move rtc-reset-reinjection and SEV in target.json and make them conditional on TARGET_I386. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190214152251.2073-10-armbru@redhat.com>
2019-02-18s390x/cpumodel: default enable mepoch for z14 and laterCollin Walling
Latest systems and host kernels support mepoch, which is a feature that was meant to be supported for z14 GA1 from the get-go. Let's copy it to the z14 GA1 default CPU model. Machines s390-ccw-virtio-3.1 and older will retain the old CPU models and will not provide this bit nor the extended PTFF functions in the default model. Signed-off-by: Collin Walling <walling@linux.ibm.com> Message-Id: <20190212011657.18324-2-walling@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-18s390x: add zPCI feature to "qemu" CPU modelDavid Hildenbrand
As we now always have PCI support, let's add it to the "qemu" CPU model, taking care of backwards compatibility. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190212112323.15904-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-18s390x: always provide pci supportCornelia Huck
We tried to make pci support optional on s390x in the past; unfortunately, we still require the s390 phb to be created unconditionally due to backwards compatibility issues. Instead of sinking more effort into this (including compat handling for older machines etc.) for non-obvious gains, let's just make CONFIG_PCI something that is always set on s390x. Note that you can still fence off pci for the _guest_ if you provide a cpu model without the zpci feature. Message-Id: <20190211113255.3837-1-cohuck@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-18xics: Drop the KVM ICS classGreg Kurz
The KVM ICS class isn't used anymore. Drop it. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <155023084177.1011724.14693955932559990358.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-18spapr/irq: Use the "simple" ICS class for KVMGreg Kurz
The "simple" ICS class knows how to interract with KVM. Adapt sPAPR to use it instead of the ICS KVM class. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <155023083585.1011724.2868047424353921455.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-18xics: Handle KVM interrupt presentation from "simple" ICS codeGreg Kurz
We want to use the "simple" ICS type in both KVM and non-KVM setups. Teach the "simple" ICS how to present interrupts to KVM and adapt sPAPR accordingly. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <155023082996.1011724.16237920586343905010.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-18xics: Handle KVM ICS reset from the "simple" ICS codeGreg Kurz
The KVM ICS reset handler simply writes the ICS state to KVM. This doesn't need the overkill parent_reset logic we have today. Also we want to use the same ICS type for the KVM and non-KVM case with pseries. Call icp_set_kvm_state() from the "simple" ICS reset function. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <155023082407.1011724.1983100830860273401.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-18xics: Explicitely call KVM ICS methods from the common codeGreg Kurz
The pre_save(), post_load() and synchronize_state() methods of the ICSStateClass type are really KVM only things. Make that obvious by dropping the indirections and directly calling the KVM functions instead. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <155023081817.1011724.14078777320394028836.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-18xics: Drop the KVM ICP classGreg Kurz
The KVM ICP class isn't used anymore. Drop it. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <155023081228.1011724.12474992370439652538.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-18spapr/irq: Use the base ICP class for KVMGreg Kurz
The base ICP class knows how to interact with KVM. Adapt sPAPR to use it instead of the ICP KVM class. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <155023080638.1011724.792095453419098948.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-18xics: Handle KVM ICP realize from the common codeGreg Kurz
The realization of KVM ICP currently follows the parent_realize logic, which is a bit overkill here. Also we want to get rid of the KVM ICP class. Explicitely call icp_kvm_realize() from the base ICP realize function. Note that ICPStateClass::parent_realize is retained because powernv needs it. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <155023080049.1011724.15423463482790260696.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-18xics: Handle KVM ICP reset from the common codeGreg Kurz
The KVM ICP reset handler simply writes the ICP state to KVM. This doesn't need the overkill parent_reset logic we have today. Call icp_set_kvm_state() from the base ICP reset function instead. Since there are no other users for ICPStateClass::parent_reset, and it isn't currently expected to change, drop it as well. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <155023079461.1011724.12644984391500635645.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-18xics: Explicitely call KVM ICP methods from the common codeGreg Kurz
The pre_save(), post_load() and synchronize_state() methods of the ICPStateClass type are really KVM only things. Make that obvious by dropping the indirections and directly calling the KVM functions instead. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <155023078871.1011724.3083923389814185598.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-17spapr/irq: remove the XICS offset adjustmentCédric Le Goater
Now that we have changed the XICS and the XIVE interrupt backend to have different size for their IRQ number space, we do not need to align their source numbers anymore. Remove the offset adjustment and wire the dual 'qirq' handler to the 'qirq' handler of the current interrupt mode in use. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190213210756.27032-3-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-17spapr/irq: add an 'nr_irq' parameter to initialize the backend.Cédric Le Goater
When using the 'dual' interrupt mode, the source numbers of both sPAPR IRQ backends are aligned to share a common IRQ number space and to use a similar mapping of the machine qemu_irq array which is indexed by the source number. The XICS IRQ number range initially being [ 0x1000 - 0x2000 ], this requires to change the XICS ICSState offset to 0 and to provision for an extra 4K of source numbers and qemu_irqs which will never be used by the machine when running under the XICS interrupt mode. This is not an optimal solution. Change the init() method to allocate an IRQ number space of the expected size for the XICS sPAPR IRQ backend. It breaks the interrupt signaling when under the 'dual' mode because source numbers have unexpected values but next patch will fix that. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190213210756.27032-2-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-17spapr: fix out of bounds write in spapr_populate_drmem_v2Fabiano Rosas
buf_len is uint8_t which is not large enough to hold the result of: nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); for a nr_entries greater than 10. This causes the allocated buffer 'int_buf' to be smaller than expected and we eventually overwrite some of glibc's control structures (see "chunk" in https://sourceware.org/glibc/wiki/MallocInternals) The following error is seen while trying to free int_buf: "free(): invalid next size (fast)" Fixes: a324d6f166 "spapr: Support ibm,dynamic-memory-v2 property" Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20190213172926.21740-1-farosas@linux.ibm.com> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-17qdev: pass an Object * to qbus_set_hotplug_handler()Michael Roth
Certain devices types, like memory/CPU, are now being handled using a hotplug interface provided by a top-level MachineClass. Hotpluggable host bridges are another such device where it makes sense to use a machine-level hotplug handler. However, unlike those devices, host-bridges have a parent bus (the main system bus), and devices with a parent bus use a different mechanism for registering their hotplug handlers: qbus_set_hotplug_handler(). This interface currently expects a handler to be a subclass of DeviceClass, but this is not the case for MachineClass, which derives directly from ObjectClass. Internally, the interface only requires an ObjectClass, so expose that in qbus_set_hotplug_handler(). Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Acked-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <154999589921.690774.3640149277362188566.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-17xive: Only set source type for LSIsGreg Kurz
MSI is the default and LSI specific code is guarded by the xive_source_irq_is_lsi() helper. The xive_source_irq_set() helper is a nop for MSIs. Simplify the code by turning xive_source_irq_set() into xive_source_irq_set_lsi() and only call it for LSIs. The call to xive_source_irq_set(false) in spapr_xive_irq_free() is also a nop. Just drop it. Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <154999584656.690774.18352404495120358613.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-17mac_newworld: change default NIC to sungem for mac99 machineMark Cave-Ayland
This model brings out-of-the-box networking for all of Linux, MacOS 9 and OS X without requiring the installation of additional drivers. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20190208172201.29001-1-mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-17spapr: Disallow unsupported kernel-irqchip settingsGreg Kurz
Split mode doesn't make sense on pseries, neither with XICS nor XIVE. But passing kernel-irqchip=split silently behaves like kernel-irqchip=on. Other architectures that support kernel-irqchip do terminate QEMU when split mode is requested but not available though. Do the same with pseries for consistency. Similarly, passing kernel-irqchip=on,accel=tcg starts the machine with the emulated interrupt controller, ie, behaves like kernel-irqchip=off. However, when passing kernel-irqchip=on,accel=kvm, if we can't initialize the KVM XICS for some reason, ie, xics_kvm_init() fails, then QEMU is terminated. This is inconsistent. Terminate QEMU all the same when requesting the in-kernel interrupt controller without KVM. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <154964986747.291716.2679312373018476920.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-17cuda: decrease time delay before raising VIA SR interrupt and remove fast pathMark Cave-Ayland
In order to handle a race condition in the MacOS 9 CUDA driver, a delay was introduced when raising the VIA SR interrupt inspired by similar code in MacOnLinux. During original testing of the MacOS 9 patches it was found that the 30us delay used in MacOnLinux did not work reliably within QEMU, and a value of 300us was required to function correctly. Recent experiments have shown two things: firstly when booting Linux, MacOS 9 and MacOS X the fast path which bypasses the delay is never triggered once the OS kernel is loaded making it effectively useless. Rather than leave this code in place where a guest could potentially enable it by accident and break itself, we might as well just remove it. Secondly the previous reliability issues are no longer present, and this value can be reduced down to 20us with no apparent ill effects. This has the benefit of considerably improving the responsiveness of the ADB keyboard and mouse within the guest. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-17spapr_pci: Fix interrupt leak in rtas_ibm_change_msi() error pathGreg Kurz
Now that IRQ allocation has been split in two (first allocate IRQ numbers, then claim them), if the claiming fails, we must release the IRQs. Fixes: 4fe75a8ccd80 "spapr: split the IRQ allocation sequence" Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-17spapr: Rename xics to intc in interrupt controller agnostic codeGreg Kurz
All this code is used with both the XICS and XIVE interrupt controllers. Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-17hw/ppc/prep: Drop useless inclusion of "hw/i386/pc.h"Philippe Mathieu-Daudé
In 47973a2dbf we split the last generic chipset out of the PC board, but forgot to remove the include of "hw/i386/pc.h". Since it is now unused, remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-15hw/arm/armsse: Fix miswiring of expansion IRQsPeter Maydell
In commit 91c1e9fcbd7548db368 where we added dual-CPU support to the ARMSSE, we set up the wiring of the expansion IRQs via nested loops: the outer loop on 'i' loops for each CPU, and the inner loop on 'j' loops for each interrupt. Fix a typo which meant we were wiring every expansion IRQ line to external IRQ 0 on CPU 0 and to external IRQ 1 on CPU 1. Fixes: 91c1e9fcbd7548db368 ("hw/arm/armsse: Support dual-CPU configuration") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-02-15hw/intc/armv7m_nvic: Allow byte accesses to SHPR1Peter Maydell
The code for handling the NVIC SHPR1 register intends to permit byte and halfword accesses (as the architecture requires). However the 'case' line for it only lists the base address of the register, so attempts to access bytes other than the first one end up in the "bad write" default logic. This bug was added accidentally when we split out the SHPR1 logic from SHPR2 and SHPR3 to support v6M. Fixes: 7c9140afd594 ("nvic: Handle ARMv6-M SCS reserved registers") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> --- The Zephyr RTOS happens to access SHPR1 byte at a time, which is how I spotted this.
2019-02-14Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-feb-14-2019' ↵Peter Maydell
into staging MIPS queue for February 14th, 2019 # gpg: Signature made Thu 14 Feb 2019 16:48:39 GMT # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-feb-14-2019: tests/tcg: target/mips: Add tests for MSA logic instructions tests/tcg: target/mips: Add wrappers for MSA logic instructions tests/tcg: target/mips: Add tests for MSA interleave instructions tests/tcg: target/mips: Add wrappers for MSA interleave instructions tests/tcg: target/mips: Add tests for MSA bit counting instructions tests/tcg: target/mips: Add wrappers for MSA bit counting instructions tests/tcg: target/mips: Add a header with test utilities tests/tcg: target/mips: Add a header with test inputs tests/tcg: target/mips: Remove an unnecessary file target/mips: introduce MTTCG-enabled builds hw/mips_cpc: kick a VP when putting it into Run statewq target/mips: hold BQL in mips_vpe_wake() hw/mips_int: hold BQL for all interrupt requests target/mips: reimplement SC instruction emulation and use cmpxchg target/mips: compare virtual addresses in LL/SC sequence Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-14Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier2/tags/trivial-branch-pull-request' into staging - some configure updates (HAX/NetBSD, remove "wav", -Waddress-of-packed-member) - remove deprecated options - some trace and error cleanup - typo fixes # gpg: Signature made Thu 14 Feb 2019 10:46:50 GMT # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-pull-request: configure: improve usbfs check hw/sparc64: Explicitly set default_display = "std" hw/dma/i8257: Use qemu_log_mask(UNIMP) instead of fprintf wavcapture: Convert to error_report kvm: Add kvm_set_ioeventfd* traces HMP: Prepend errors with 'Error:' pckbd: Convert DPRINTF->trace configure: Make -Waddress-of-packed-member warnings be errors configure: Add HAX support in NetBSD configure: fix qemu-img name configure: remove handling of "wav" audio driver qemu-options: Remove deprecated option -clock qemu-deprecated: Remove -virtioconsole and -no-frame for good qapi: Fix qcow2 encryption doc typo Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-14hw/mips_cpc: kick a VP when putting it into Run statewqMiodrag Dinic
While testing mttcg VP0 could get stuck in a loop waiting for other VPs to come up (which never actually happens). To fix this, kick VPs while they are being powered up by Cluster Power Controller in an async task which is triggered once the host thread is being spawned. Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2019-02-14hw/mips_int: hold BQL for all interrupt requestsAleksandar Markovic
Make sure BQL is held for all interrupt requests. For MTTCG-enabled configurations, handling soft and hard interrupts between vCPUs must be properly locked. By acquiring BQL, make sure all paths triggering an IRQ are synchronized. Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2019-02-14Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell
staging Pull request Fix a virtio-blk migration regression. # gpg: Signature made Thu 14 Feb 2019 04:32:55 GMT # gpg: using RSA key 9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: virtio-blk: set correct config size for the host driver Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-14Merge remote-tracking branch 'remotes/elmarco/tags/chardev-pull-request' ↵Peter Maydell
into staging Chardev fixes # gpg: Signature made Wed 13 Feb 2019 16:18:36 GMT # gpg: using RSA key DAE8E10975969CE5 # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full] # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full] # Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5 * remotes/elmarco/tags/chardev-pull-request: (25 commits) char-pty: remove write_lock usage char-pty: remove the check for connection on write chardev: add a note about frontend sources and context switch terminal3270: do not use backend timer sources char: update the mux handlers in class callback chardev/wctablet: Fix a typo char: allow specifying a GMainContext at opening time chardev: ensure termios is fully initialized tests: expand coverage of socket chardev test chardev: fix race with client connections in tcp_chr_wait_connected chardev: disallow TLS/telnet/websocket with tcp_chr_wait_connected chardev: honour the reconnect setting in tcp_chr_wait_connected chardev: use a state machine for socket connection state chardev: split up qmp_chardev_open_socket connection code chardev: split tcp_chr_wait_connected into two methods chardev: remove unused 'sioc' variable & cleanup paths chardev: ensure qemu_chr_parse_compat reports missing driver error chardev: remove many local variables in qemu_chr_parse_socket chardev: forbid 'wait' option with client sockets chardev: forbid 'reconnect' option with server sockets ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-14Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-sf1' ↵Peter Maydell
into staging RISC-V Patches for the 4.0 Soft Freeze, Part 1 This patch set contains a handful of patches I've collected over the last few weeks. There's nothing really fundamental, but I thought it would be good to send these out now as there are some other patch sets on the mailing list that are getting ready to go. As far as the actual patches, there's: * A set that cleans up our FS dirty-mode handling. * Support for writing MISA. * The removal of Michael as a maintainer. * A fix to {m,s}counteren handling. * A fix to make sure the kernel's start address is computed correctly on 32-bit targets. This makes my "RISC-V Patches for 3.2, Part 3" pull request defunct, as it contains the same patches but based on a newer master. As usual, I've tested this using a Fedora boot on the latest Linux. This patch set does not include Bastian's decodetree patches because there were some merge conflicts and while I've cleaned them up I want to get a round of review first. # gpg: Signature made Wed 13 Feb 2019 15:37:50 GMT # gpg: using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 * remotes/palmer/tags/riscv-for-master-4.0-sf1: riscv: Ensure the kernel start address is correctly cast target/riscv: fix counter-enable checks in ctr() MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer RISC-V: Add misa runtime write support RISC-V: Add misa.MAFD checks to translate RISC-V: Add misa to DisasContext RISC-V: Add priv_ver to DisasContext RISC-V: Use riscv prefix consistently on cpu helpers RISC-V: Implement mstatus.TSR/TW/TVM RISC-V: Mark mstatus.fs dirty RISC-V: Split out mstatus_fs from tb_flags Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-14hw/sparc64: Explicitly set default_display = "std"Thomas Huth
The sun4uv_init() function expects vga_interface_type to be either VGA_STD or VGA_NONE and sets up a stdvga device or no vga card accordingly. However, the code in vl.c prefers the Cirrus VGA card to stdvga if it is available and the user and the machine did not specify anything else. So far this has not been a problem, since the Cirrus VGA was not linked into the sparc64 target. But with the upcoming Kconfig build system, all theoretically possible PCI cards will be enabled by default, so the Cirrus VGA card might become available on the sparc64 target, too. vl.c then picks the wrong card, causing sun4uv_init() to abort. Thus let's make it explicit that we always want stdvga for sparc64 and so set default_display = "std" for these machines. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <1550041639-10232-1-git-send-email-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-02-14hw/dma/i8257: Use qemu_log_mask(UNIMP) instead of fprintfPhilippe Mathieu-Daudé
Avoid to clutter stdout until explicitly requested (with -d unimp): $ qemu-system-mips64el -M fulong2e -bios pmon_2e.bin dma: command df not supported dma: command df not supported dma: command df not supported dma: command df not supported Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Message-Id: <20190212145322.30974-1-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-02-14pckbd: Convert DPRINTF->traceDr. David Alan Gilbert
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20181016112232.23241-1-dgilbert@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-02-13terminal3270: do not use backend timer sourcesMarc-André Lureau
terminal3270 uses the front-end side of the chardev. It shouldn't create sources from backend side context (with backend functions). send_timing_mark_cb calls qemu_chr_fe_write_all() which should be thread safe. This partially reverts changes from commit 2c716ba1506769c9be2caa02f0f6d6e7c00f4304. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20190206174328.9736-4-marcandre.lureau@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2019-02-13char: allow specifying a GMainContext at opening timePaolo Bonzini
This will be needed by vhost-user-test, when each test switches to its own GMainLoop and GMainContext. Otherwise, for a reconnecting socket the initial connection will happen on the default GMainContext, and no one will be listening on it. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20190202110834.24880-1-pbonzini@redhat.com> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
2019-02-13virtio-blk: set correct config size for the host driverChangpeng Liu
Commit caa1ee43 "vhost-user-blk: add discard/write zeroes features support" added fields to struct virtio_blk_config. This changes the size of the config space and breaks migration from QEMU 3.1 and older: qemu-system-ppc64: get_pci_config_device: Bad config data: i=0x10 read: 41 device: 1 cmask: ff wmask: 80 w1cmask:0 qemu-system-ppc64: Failed to load PCIDevice:config qemu-system-ppc64: Failed to load virtio-blk:virtio qemu-system-ppc64: error while loading state for instance 0x0 of device 'pci@800000020000000:01.0/virtio-blk' qemu-system-ppc64: load of migration failed: Invalid argument Since virtio-blk doesn't support the "discard" and "write zeroes" features, it shouldn't even expose the associated fields in the config space actually. Just include all fields up to num_queues to match QEMU 3.1 and older. Signed-off-by: Changpeng Liu <changpeng.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 1550022537-27565-1-git-send-email-changpeng.liu@intel.com Message-Id: <1550022537-27565-1-git-send-email-changpeng.liu@intel.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2019-02-12hw/hppa: forward requests to CPU HPASven Schnelle
HP-UX 10.20 uses busmaster writes to the CPU EIR to signal interrupts from the SCSI constroller. (Similar to what is known as MSI on x86) Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190211192039.5457-1-svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-12virtio-blk: cleanup using VirtIOBlock *s and VirtIODevice *vdevStefano Garzarella
In several part we still using req->dev or VIRTIO_DEVICE(req->dev) when we have already defined s and vdev pointers: VirtIOBlock *s = req->dev; VirtIODevice *vdev = VIRTIO_DEVICE(s); Signed-off-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Liam Merwick <liam.merwick@oracle.com> Message-id: 20190208142347.214815-1-sgarzare@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2019-02-11riscv: Ensure the kernel start address is correctly castAlistair Francis
Cast the kernel start address to the target bit length. This ensures that we calculate the initrd offset to a valid address for the architecture. Steps to reproduce the original problem (reported by Alex): Build U-Boot for the virt machine for riscv32. Then run it with $ qemu-system-riscv32 -M virt -kernel u-boot -nographic -initrd <a file> You can find the initrd address with U-Boot# fdt addr $fdtcontroladdr U-Boot# fdt ls /chosen Then take a peek at that address: U-Boot# md.b <addr> and you will see that there is nothing there without this patch. The reason is that the binary was loaded to a negative address. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Suggested-by: Alexander Graf <agraf@suse.de> Reported-by: Alexander Graf <agraf@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-07Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-20190206' ↵Peter Maydell
into staging qemu-sparc queue # gpg: Signature made Wed 06 Feb 2019 21:25:18 GMT # gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F # gpg: issuer "mark.cave-ayland@ilande.co.uk" # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full] # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/qemu-sparc-20190206: sun4m: pass initrd size to OpenBIOS via fw_cfg interface sun4u: add power_mem_read routine hw/sparc64: Create VGA device only if it has really been requested Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-07Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier2/tags/trivial-patches-pull-request' into staging Trivial patches: * Update copyright * Fix LGPL in target/moxie * configure portability fix * Drop useless inclusion of "hw/i386/pc.h" * Mark the cpu-cluster device with user_creatable = false * tsc210x: Fix building with no verbosity # gpg: Signature made Wed 06 Feb 2019 15:27:35 GMT # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-patches-pull-request: hw/input/tsc210x: Fix building with no verbosity hw/cpu/cluster: Mark the cpu-cluster device with user_creatable = false hw/unicore32/puv3: Drop useless inclusion of "hw/i386/pc.h" hw/sparc64/sun4u: Drop useless inclusion of "hw/i386/pc.h" configure: Avoid non-portable 'test -o/-a' target/moxie: Fix LGPL information in the file headers qemu-common.h: Update copyright string for 2019 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-06sun4m: pass initrd size to OpenBIOS via fw_cfg interfaceMark Cave-Ayland
This is to enable OpenBIOS to claim the initrd memory as in-use before attempting to boot the kernel. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-12 14:00:43 +0000