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2016-04-07virtio-blk: fix disabled modePaolo Bonzini
We must not call virtio_blk_data_plane_notify if dataplane is disabled: we would hit a segmentation fault in notify_guest_bh as s->guest_notifier has not been setup and is NULL. Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-04-07virtio: make virtio_queue_notify_vq staticPaolo Bonzini
Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-04-07virtio-balloon: reset the statistic timer to load devicePavel Butsykin
If before loading snapshot we had set the timer of statistics, then after applying snapshot the expiry time would be irrelevant for the restored state of the virtual clocks. A simple fix is just to restart the timer after loading snapshot. For the user it may look like a long delay of statistics update after switch to the snapshot. Signed-off-by: Pavel Butsykin <pbutsykin@virtuozzo.com> Reviewed-by: Roman Kagan <rkagan@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-04-07Migration: Add i82801b11 migration dataDr. David Alan Gilbert
The i82801b11 bridge didn't have a vmsd and thus didn't send any migration data, including that of its parent PCIBridge object. The symptom being if the guest used any devices behind the bridge the guest crashed (mostly with various interrupt related issues). Note: This will cause migration from old qemus that used this device to explicitly fail during migration as opposed to the guest crashing. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Suggested-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-04-07Sort the fw_cfg file listGerd Hoffmann
Entries are inserted in filename order instead of being appended to the end in case sorting is enabled. This will avoid any future issues of moving the file creation around, it doesn't matter what order they are created now, the will always be in filename order. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Added machine type handling for compatibility. This was a fairly complex change, this will preserve the order of fw_cfg for older versions no matter what order the firmware files actually come in. A list is kept of the correct legacy order and the entries will be inserted based upon their order in the list. Except that some entries are ordered (in a specific area of the list) based upon what order they appear on the command line. Special handling is added for those entries. Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-04-07xen: piix reuse pci generic class init functionMichael S. Tsirkin
piix3_ide_xen_class_init is identical to piix3_ide_class_init except it's buggy as it does not set exit and does not disable hotplug properly. Switch to the generic one. Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-04-07pci-testdev: fast mmio supportMichael S. Tsirkin
Teach PCI testdev to use fast MMIO when kvm makes it available. Before: mmio-wildcard-eventfd:pci-mem 2271 After: mmio-wildcard-eventfd:pci-mem 1218 Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-04-06rtl8139: using CP_TX_OWN for ownership transferring during txJason Wang
Through CP_TX_OWN and CP_RX_OWN points to the same bit, we'd better use CP_TX_OWN for tx descriptor handling. Signed-off-by: Jason Wang <jasowang@redhat.com>
2016-04-05spapr_drc: enable immediate detach for unsignalled devicesMichael Roth
Currently spapr doesn't support "aborting" hotplug of PCI devices by allowing device_del to immediately remove the device if we haven't signalled the presence of the device to the guest. In the past this wasn't an issue, since we always immediately signalled device attach and simply relied on full guest-aware add->remove path for device removal. However, as of 788d259, we now defer signalling for PCI functions until function 0 is attached, so now we need to deal with these "abort" operations for cases where a user hotplugs a non-0 function, then opts to remove it prior hotplugging function 0. Currently they'd have to reboot before the unplug completed. PCIe multifunction hotplug does not have this requirement however, so from a management implementation perspective it would be good to address this within the same release as 788d259. We accomplish this by simply adding a 'signalled' flag to track whether a device hotplug event has been sent to the guest. If it hasn't, we allow immediate removal under the assumption that the guest will not be using the device. Devices present at boot/reset time are also assumed to be 'signalled'. For CPU/memory/etc, signalling will still happen immediately as part of device_add, so only PCI functions should be affected. Cc: bharata@linux.vnet.ibm.com Cc: david@gibson.dropbear.id.au Cc: sbhat@linux.vnet.ibm.com Cc: qemu-ppc@nongnu.org Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com> [dwg: This fixes a regression where an incorrect hot-add of a non-zero function can no longer be backed out until function 0 is added] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-04-05ppc: Rework POWER7 & POWER8 exception modelCédric Le Goater
From: Benjamin Herrenschmidt <benh@kernel.crashing.org> This patch fixes the current AIL implementation for POWER8. The interrupt vector address can be calculated directly from LPCR when the exception is handled. The excp_prefix update becomes useless and we can cleanup the H_SET_MODE hcall. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: Removed LPES0/1 handling for HV vs. !HV Fixed LPCR_ILE case for POWERPC_EXCP_POWER8 ] Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> [dwg: This was written as a cleanup, but it also fixes a real bug where setting an alternative interrupt location would not be correctly migrated] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-04-04hw/arm/bcm2836: Wire up CPU timer interrupts correctlyPeter Maydell
Wire up the CPU timer interrupts in the right order, with the nonsecure physical timer on cntpnsirq, the hyp timer on cnthpirq, and the secure physical timer on cntpsirq. (We did get the virt timer right, at least.) Reported-by: Antonio Huete Jiménez <tuxillo@quantumachine.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1458210790-6621-1-git-send-email-peter.maydell@linaro.org
2016-04-04opencores_eth: indicate autonegotiation completionMax Filippov
Indicate that autonegotiation is complete in the MII BMSR. This fixes networking on xtfpga platform in linux v4.5. Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2016-03-30block: m25p80: at25128a/at25256a modelsMarcin Krzeminski
Signed-off-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 1458719789-29868-12-git-send-email-marcin.krzeminski@nokia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-30block: m25p80: n25q256a/n25q512a modelsMarcin Krzeminski
Signed-off-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 1458719789-29868-11-git-send-email-marcin.krzeminski@nokia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-30block: m25p80: Implemented FSR registerMarcin Krzeminski
Implements FSR register, it is used for busy waits. Signed-off-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 1458719789-29868-10-git-send-email-marcin.krzeminski@nokia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-30block: m25p80: Fast read and 4bytes commandsMarcin Krzeminski
Adds fast read and 4bytes commands family. This work is based on Pawel Lenkow patch from v1. Signed-off-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 1458719789-29868-9-git-send-email-marcin.krzeminski@nokia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-30block: m25p80: Dummy cycles for N25Q256/512Marcin Krzeminski
Use the setting from the volatile cfg register to correctly set the number of dummy cycles. Signed-off-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 1458719789-29868-8-git-send-email-marcin.krzeminski@nokia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-30block: m25p80: Add configuration registersMarcin Krzeminski
This patch adds both volatile and non volatile configuration registers and commands to allow modify them. It is needed for proper handling dummy cycles. Initialization of those registers and flash state has been included as well. Some of this registers are used by kernel. Signed-off-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Acked-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 1458719789-29868-7-git-send-email-marcin.krzeminski@nokia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-30block: m25p80: 4byte address modeMarcin Krzeminski
This patch adds only 4byte address mode (does not cover dummy cycles). This mode is needed to access more than 16 MiB of flash. Signed-off-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 1458719789-29868-6-git-send-email-marcin.krzeminski@nokia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-30block: m25p80: Extend address modeMarcin Krzeminski
Extend address mode allows to switch flash 16 MiB banks, allowing user to access all flash sectors. This access mode is used by u-boot. Signed-off-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 1458719789-29868-5-git-send-email-marcin.krzeminski@nokia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-30block: m25p80: Widen flags variableMarcin Krzeminski
Extend the width of the flags variable to support the already existing (but unused) WR_1 flag, which is above the range of 8 bits. This allows support of EEPROM emulation which requires the WR_1 feature. Signed-off-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 1458719789-29868-4-git-send-email-marcin.krzeminski@nokia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-30block: m25p80: RESET_ENABLE and RESET_MEMORY commandsMarcin Krzeminski
Signed-off-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 1458719789-29868-3-git-send-email-marcin.krzeminski@nokia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-30block: m25p80: Removed unused variableMarcin Krzeminski
Signed-off-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 1458719789-29868-2-git-send-email-marcin.krzeminski@nokia.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-30ARM: Virt: Use gpio_key for power buttonShannon Zhao
There is a problem for power button that it will not work if an early system_powerdown request happens before guest gpio driver loads. Fix this problem by using gpio_key. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1458221140-15232-3-git-send-email-zhaoshenglong@huawei.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-30hw/gpio: Add the emulation of gpio_keyShannon Zhao
This will be used by ARM virt machine as a power button. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1458221140-15232-2-git-send-email-zhaoshenglong@huawei.com [PMM: Use hyphen rather than underscore in type names; add a comment briefly describing what the device does] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-30Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160329-2' into stagingPeter Maydell
MIPS patches 2016-03-29 Changes: * add initial MIPS CPS support * implement ITU block * implement MAAR # gpg: Signature made Wed 30 Mar 2016 09:27:01 BST using RSA key ID 0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" * remotes/lalrae/tags/mips-20160329-2: (21 commits) target-mips: add MAAR, MAARI register target-mips: use CP0_CHECK for gen_m{f|t}hc0 hw/mips/cps: enable ITU for multithreading processors target-mips: make ITC Configuration Tags accessible to the CPU target-mips: check CP0 enabled for CACHE instruction also in R6 hw/mips: implement ITC Storage - Bypass View hw/mips: implement ITC Storage - P/V Sync and Try Views hw/mips: implement ITC Storage - Empty/Full Sync and Try Views hw/mips: implement ITC Storage - Control View hw/mips: implement ITC Configuration Tags and Storage Cells target-mips: enable CM GCR in MIPS64R6-generic CPU hw/mips_malta: add CPS to Malta board hw/mips_malta: move CPU creation to a separate function hw/mips_malta: remove redundant irq and clock init hw/mips_malta: remove CPUMIPSState from the write_bootloader() hw/mips/cps: create CPC block inside CPS hw/mips: add initial Cluster Power Controller support hw/mips/cps: create GCR block inside CPS hw/mips: add initial Global Config Register support target-mips: add CMGCRBase register ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-30Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell
Block layer patches # gpg: Signature made Wed 30 Mar 2016 11:57:54 BST using RSA key ID C88F2FD6 # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" * remotes/kevin/tags/for-upstream: (48 commits) iotests: Test qemu-img convert -S 0 behavior block/null-{co,aio}: Implement get_block_status() block/null-{co,aio}: Allow reading zeroes qemu-img: Fix preallocation with -S 0 for convert block: Remove bdrv_(set_)enable_write_cache() block: Remove BDRV_O_CACHE_WB block: Remove bdrv_parse_cache_flags() qemu-io: Use bdrv_parse_cache_mode() in reopen_f() block: Use bdrv_parse_cache_mode() in drive_init() raw: Support BDRV_REQ_FUA nbd: Support BDRV_REQ_FUA iscsi: Support BDRV_REQ_FUA block: Introduce bdrv_co_writev_flags() block/qapi: Use blk_enable_write_cache() block: Move enable_write_cache to BB level block: Handle flush error in bdrv_pwrite_sync() block: Always set writeback mode in blk_new_open() block: blockdev_init(): Call blk_set_enable_write_cache() explicitly xen_disk: Call blk_set_enable_write_cache() explicitly qemu-img: Call blk_set_enable_write_cache() explicitly ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-30xen_disk: Call blk_set_enable_write_cache() explicitlyKevin Wolf
Signed-off-by: Kevin Wolf <kwolf@redhat.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Max Reitz <mreitz@redhat.com>
2016-03-30hw/mips/cps: enable ITU for multithreading processorsLeon Alrae
Make ITU available in the system if CPU supports multithreading and is part of CPS. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips: implement ITC Storage - Bypass ViewLeon Alrae
Bypass View does not cause issuing thread to block and does not affect any of the cells state bit. Read from a FIFO cell returns the value of the oldest entry. Store to a FIFO cell changes the value of the newest entry. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips: implement ITC Storage - P/V Sync and Try ViewsLeon Alrae
P/V Synchronized and Try Views can be used to access Semaphore cells. Load returns current value and post-decrements the value in the cell (until it reaches zero). Stores increment the value (until it saturates at 0xFFFF). P/V Synchronized View causes the issuing thread to block on read if value is 0. P/V Try View does not block the thread, it returns 0 in this case. Cell's Empty and Full bits are not modified. Trap bit (i.e. Gating Storage exceptions) not implemented. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips: implement ITC Storage - Empty/Full Sync and Try ViewsLeon Alrae
Empty/Full Synchronized and Try views can be used to access FIFO cells. Store to the FIFO cell pushes the value into the queue, load pops the oldest element from the queue. Cell's Full and Empty bits are automatically updated to reflect new state of the cell. Empty/Full Synchronized View causes the issuing thread to block when FIFO is empty while thread is performing a read, or FIFO is full while thread is performing a write. Empty/Full Try View never blocks the thread. If cell is full then write is ignored, if cell is empty then load returns 0. Trap bit (i.e. Gating Storage exceptions) not implemented. Store Conditional support for E/F Try View (i.e. indicate failure if FIFO is full) not implemented. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips: implement ITC Storage - Control ViewLeon Alrae
Control view is used to access the ITC Storage Cell Tags. It never causes the issuing thread to block. Guest can empty the FIFO cell by setting Empty bit to 1. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips: implement ITC Configuration Tags and Storage CellsLeon Alrae
Implement ITC as a single object consisting of two memory regions: 1) tag_io: ITC Configuration Tags (i.e. ITCAddressMap{0,1} registers) which are accessible by the CPU via CACHE instruction. Also adding MemoryRegion *itc_tag to the CPUMIPSState so that CACHE instruction will dispatch reads/writes directly. 2) storage_io: memory-mapped ITC Storage whose address space is configurable (i.e. enabled/remapped/resized) by writing to ITCAddressMap{0,1} registers. ITC Storage contains FIFO and Semaphore cells. Read-only FIFO bit in the ITC cell tag indicates the type of the cell. If the ITC Storage contains both types of cells then FIFOs are located before Semaphores. Since issuing thread can get blocked on the access to a cell (in E/F Synchronized and P/V Synchronized Views) each cell has a bitmap to track which threads are currently blocked. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips_malta: add CPS to Malta boardLeon Alrae
If the user specifies smp > 1 and the CPU with CM GCR support, then create Coherent Processing System (which takes care of instantiating CPUs) rather than CPUs directly and connect i8259 and cbus to the pins exposed by CPS. However, there is no GIC yet, thus CPS exposes CPU's IRQ pins so use the same pin numbers as before. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips_malta: move CPU creation to a separate functionLeon Alrae
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips_malta: remove redundant irq and clock initLeon Alrae
Global smp_cpus is never zero (even if user provides -smp 0), thus clocks and irqs are always initialized for each created CPU in the loop at the beginning of mips_malta_init. These two lines cause a leak of already allocated timer and irqs for the first CPU - remove them. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips_malta: remove CPUMIPSState from the write_bootloader()Leon Alrae
Remove CPUMIPSState from the write_bootloader() argument list as it is not used in the function. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips/cps: create CPC block inside CPSLeon Alrae
Create Cluster Power Controller and add a link to the CPC MemoryRegion in GCR. Guest can enable / map CPC to any physical address by writing to the memory-mapped GCR_CPC_BASE register. Set vp-start-reset property to 1 to allow only first VP to run from reset. Others are brought up by the guest via CPC memory-mapped registers. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips: add initial Cluster Power Controller supportLeon Alrae
Cluster Power Controller (CPC) is responsible for power management in multiprocessing system. It provides registers to control the power and the clock frequency of the individual elements in the system. This patch implements only three registers that are used to control the power state of each VP on a single core: * VP Run is a write-only register used to set each VP to the run state * VP Stop is a write-only register used to set each VP to the suspend state * VP Running is a read-only register indicating the run state of each VP Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips/cps: create GCR block inside CPSLeon Alrae
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips: add initial Global Config Register supportYongbok Kim
Add initial GCR support to indicate number of VPs present in the system, L2 bypass mode and revision number. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> [leon.alrae@imgtec.com: * removed GIC part, * changed commit message, * replaced %lx format spec. with PRIx64, * renamed mips_gcr.{c,h} to mips_cmgcr.{c,h}, * replaced CONFIG_MIPS_GIC with CONFIG_MIPS_CPS] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips: implement generic MIPS Coherent Processing System containerLeon Alrae
Implement generic MIPS Coherent Processing System (CPS) which in this commit just creates VPs, but it will serve as a container also for other components like Global Configuration Registers and Cluster Power Controller. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30Revert "e1000: fix hang of win2k12 shutdown with flood ping"Sameeh Jubran
This reverts commit 9596ef7c7b8528bedb240792ea1fb598543ad3c4. This workaround in order to fix endless interrupts is no longer needed because it was superseded by the previous patch (e1000: Fixing interrupt pace). Signed-off-by: Sameeh Jubran <sameeh@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2016-03-30e1000: Fixing interrupts pace.Sameeh Jubran
This patch introduces an upper bound for number of interrupts per second. Without this bound an interrupt storm can occur as it has been observed on Windows 10 when disabling the device. According to the SPEC - Intel PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual, section 13.4.18 - the Ethernet controller guarantees a maximum observable interrupt rate of 7813 interrupts/sec. If there is no upper bound this could lead to an interrupt storm by e1000 (when mit_delay < 500) causing interrupts to fire at a very high pace. Thus if mit_delay < 500 then the delay should be set to the minimum delay possible which is 500. This can be calculated easily as follows: Interval = 10^9 / (7813 * 256) = 500. Signed-off-by: Sameeh Jubran <sameeh@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2016-03-29Merge remote-tracking branch 'remotes/awilliam/tags/vfio-update-20160328.0' ↵Peter Maydell
into staging VFIO updates 2016-03-28 - Use 128bit math to avoid asserts with IOMMU regions (Bandan Das) # gpg: Signature made Mon 28 Mar 2016 23:16:52 BST using RSA key ID 3BB08B22 # gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>" # gpg: aka "Alex Williamson <alex@shazbot.org>" # gpg: aka "Alex Williamson <alwillia@redhat.com>" # gpg: aka "Alex Williamson <alex.l.williamson@gmail.com>" * remotes/awilliam/tags/vfio-update-20160328.0: vfio: convert to 128 bit arithmetic calculations when adding mem regions Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-28vfio: convert to 128 bit arithmetic calculations when adding mem regionsBandan Das
vfio_listener_region_add for a iommu mr results in an overflow assert since iommu memory region is initialized with UINT64_MAX. Convert calculations to 128 bit arithmetic for iommu memory regions and let int128_get64 assert for non iommu regions if there's an overflow. Suggested-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bandan Das <bsd@redhat.com> [missed (end - 1) on 2nd trace call, move llsize closer to use] Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2016-03-24Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* Log filtering from Alex and Peter * Chardev fix from Marc-André * config.status tweak from David * Header file tweaks from Markus, myself and Veronia (Outreachy candidate) * get_ticks_per_sec() removal from Rutuja (Outreachy candidate) * Coverity fix from myself * PKE implementation from myself, based on rth's XSAVE support # gpg: Signature made Thu 24 Mar 2016 20:15:11 GMT using RSA key ID 78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" * remotes/bonzini/tags/for-upstream: (28 commits) target-i386: implement PKE for TCG config.status: Pass extra parameters char: translate from QIOChannel error to errno exec: fix error handling in file_ram_alloc cputlb: modernise the debug support qemu-log: support simple pid substitution for logs target-arm: dfilter support for in_asm qemu-log: dfilter-ise exec, out_asm, op and opt_op qemu-log: new option -dfilter to limit output qemu-log: Improve the "exec" TB execution logging qemu-log: Avoid function call for disabled qemu_log_mask logging qemu-log: correct help text for -d cpu tcg: pass down TranslationBlock to tcg_code_gen util: move declarations out of qemu-common.h Replaced get_tick_per_sec() by NANOSECONDS_PER_SECOND hw: explicitly include qemu-common.h and cpu.h include/crypto: Include qapi-types.h or qemu/bswap.h instead of qemu-common.h isa: Move DMA_transfer_handler from qemu-common.h to hw/isa/isa.h Move ParallelIOArg from qemu-common.h to sysemu/char.h Move QEMU_ALIGN_*() from qemu-common.h to qemu/osdep.h ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Conflicts: scripts/clean-includes
2016-03-24hw/net/spapr_llan: Enable the RX buffer pools by default for new machinesThomas Huth
RX buffer pools are now enabled by default for new machine types. For older machine types, they are still disabled to avoid breaking migration. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-03-24hw/net/spapr_llan: Fix receive buffer handling for better performanceThomas Huth
tl;dr: This patch introduces an alternate way of handling the receive buffers of the spapr-vlan device, resulting in much better receive performance for the guest. Full story: One of our testers recently discovered that the performance of the spapr-vlan device is very poor compared to other NICs, and that a simple "ping -i 0.2 -s 65507 someip" in the guest can result in more than 50% lost ping packets (especially with older guest kernels < 3.17). After doing some analysis, it was clear that there is a problem with the way we handle the receive buffers in spapr_llan.c: The ibmveth driver of the guest Linux kernel tries to add a lot of buffers into several buffer pools (with 512, 2048 and 65536 byte sizes by default, but it can be changed via the entries in the /sys/devices/vio/1000/pool* directories of the guest). However, the spapr-vlan device of QEMU only tries to squeeze all receive buffer descriptors into one single page which has been supplied by the guest during the H_REGISTER_LOGICAL_LAN call, without taking care of different buffer sizes. This has two bad effects: First, only a very limited number of buffer descriptors is accepted at all. Second, we also hand 64k buffers to the guest even if the 2k buffers would fit better - and this results in dropped packets in the IP layer of the guest since too much skbuf memory is used. Though it seems at a first glance like PAPR says that we should store the receive buffer descriptors in the page that is supplied during the H_REGISTER_LOGICAL_LAN call, chapter 16.4.1.2 in the LoPAPR spec declares that "the contents of these descriptors are architecturally opaque, none of these descriptors are manipulated by code above the architected interfaces". That means we don't have to store the RX buffer descriptors in this page, but can also manage the receive buffers at the hypervisor level only. This is now what we are doing here: Introducing proper RX buffer pools which are also sorted by size of the buffers, so we can hand out a buffer with the best fitting size when a packet has been received. To avoid problems with migration from/to older version of QEMU, the old behavior is also retained and enabled by default. The new buffer management has to be enabled via a new "use-rx-buffer-pools" property. Now with the new buffer pool management enabled, the problem with "ping -s 65507" is fixed for me, and the throughput of a simple test with wget increases from creeping 3MB/s up to 20MB/s! Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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