aboutsummaryrefslogtreecommitdiff
path: root/hw
AgeCommit message (Collapse)Author
2022-05-02hw: aspeed_scu: Add AST2600 apb_freq and hpll calculation functionSteven Lee
AST2600's HPLL register offset and bit definition are different from AST2500. Add a hpll calculation function and an apb frequency calculation function based on SCU200 register description in ast2600v11.pdf. Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: checkpatch fixes ] Message-Id: <20220315075753.8591-2-steven_lee@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-05-019pfs: fix qemu_mknodat() to always return -1 on error on macOS hostChristian Schoenebeck
qemu_mknodat() is expected to behave according to its POSIX API, and therefore should always return exactly -1 on any error, and errno should be set for the actual error code. Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> Message-Id: <c714b5e1cae225ab7575242c45ee0fe4945eb6ad.1651228001.git.qemu_oss@crudebyte.com>
2022-05-019pfs: fix removing non-existent POSIX ACL xattr on macOS hostChristian Schoenebeck
When mapped POSIX ACL is used, we are ignoring errors when trying to remove a POSIX ACL xattr that does not exist. On Linux hosts we would get ENODATA in such cases, on macOS hosts however we get ENOATTR instead. As we can be sure that ENOATTR is defined as being identical on Linux hosts (at least by qemu/xattr.h), it is safe to fix this issue by simply comparing against ENOATTR instead of ENODATA. This patch fixes e.g. a command on Linux guest like: cp --preserve=mode old new Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Link: https://lore.kernel.org/qemu-devel/2866993.yOYK24bMf6@silver/ Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> Message-Id: <34f81e9bffd7a3e65fb7aab5b56c107bd0aac960.1651228001.git.qemu_oss@crudebyte.com>
2022-05-019pfs: fix wrong errno being sent to Linux client on macOS hostChristian Schoenebeck
Linux and macOS only share some errno definitions with equal macro name and value. In fact most mappings for errno are completely different on the two systems. This patch converts some important errno values from macOS host to corresponding Linux errno values before eventually sending such error codes along with 'Rlerror' replies (if 9p2000.L is used that is). Not having translated errnos before violated the 9p2000.L protocol spec, which says: " size[4] Rlerror tag[2] ecode[4] ... ecode is a numerical Linux errno. " https://github.com/chaos/diod/wiki/protocol#lerror----return-error-code This patch fixes a bunch of misbehaviours when running a Linux client on macOS host. For instance this patch fixes: mount -t 9p -o posixacl ... on Linux guest if security_mode=mapped was used for 9p server, which refused to mount successfully, because macOS returned ENOATTR==93 when client tried to retrieve POSIX ACL xattrs, because errno 93 is defined as EPROTONOSUPPORT==93 on Linux, so Linux client believed that xattrs were not supported by filesystem on host in general. Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Link: https://lore.kernel.org/qemu-devel/20220421124835.3e664669@bahia/ Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> Message-Id: <b322ab298a62069e527d2b032028bdc9115afacd.1651228001.git.qemu_oss@crudebyte.com>
2022-05-019pfs: fix wrong encoding of rdev field in Rgetattr on macOSChristian Schoenebeck
The 'rdev' field in 9p reponse 'Rgetattr' is of type dev_t, which is actually a system dependant type and therefore both the size and encoding of dev_t differ between macOS and Linux. So far we have sent 'rdev' to guest in host's dev_t format as-is, which caused devices to appear with wrong device numbers on guests running on macOS hosts, eventually leading to various misbehaviours on guest in conjunction with device files. This patch fixes this issue by converting the device number from host's dev_t format to Linux dev_t format. As 9p request 'Tgettattr' is exclusive to protocol version 9p2000.L, it should be fair to assume that 'rdev' field is assumed to be in Linux dev_t format by client as well. Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Link: https://lore.kernel.org/qemu-devel/20220421093056.5ab1e7ed@bahia/ Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> Message-Id: <b3a430c2c382ba69a7405e04c0b090ab0d86f17e.1651228001.git.qemu_oss@crudebyte.com>
2022-05-019pfs: fix qemu_mknodat(S_IFSOCK) on macOSChristian Schoenebeck
mknod() on macOS does not support creating sockets, so divert to call sequence socket(), bind() and fchmodat() respectively if S_IFSOCK was passed with mode argument. Link: https://lore.kernel.org/qemu-devel/17933734.zYzKuhC07K@silver/ Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> Message-Id: <2e7b5ecd7a6d83a538db4e8a22d8fb03e9e0f06e.1651228001.git.qemu_oss@crudebyte.com> [C.S. - Use AT_SYMLINK_NOFOLLOW instead of AT_SYMLINK_NOFOLLOW_ANY. ] Link: https://lore.kernel.org/qemu-devel/3704033.BMyLRrx2Jx@silver/
2022-04-309pfs: fix qemu_mknodat(S_IFREG) on macOSChristian Schoenebeck
mknod() on macOS does not support creating regular files, so divert to openat_file() if S_IFREG is passed with mode argument. Furthermore, 'man 2 mknodat' on Linux says: "Zero file type is equivalent to type S_IFREG". Link: https://lore.kernel.org/qemu-devel/17933734.zYzKuhC07K@silver/ Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Will Cohen <wwcohen@gmail.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> Message-Id: <3102ca936f88bc1f79d2a325e5bc68f48f54e6e3.1651228000.git.qemu_oss@crudebyte.com>
2022-04-309pfs: fix inode sequencing in 'synth' driverChristian Schoenebeck
The 'synth' driver's root node and the 'synth' driver's first subdirectory node falsely share the same inode number (zero), which makes it impossible for 9p clients (i.e. 9p test cases) to distinguish root node and first subdirectory from each other by comparing their QIDs (which are derived by 9p server from driver's inode numbers). Fix this issue by using prefix-increment instead of postfix-increment operator while generating new inode numbers for subdirectories and files. Link: https://lore.kernel.org/qemu-devel/3859307.hTDP4D0zbi@silver/ Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <E1nTpyU-0000yR-9o@lizzy.crudebyte.com>
2022-04-29hw/riscv: Enable TPM backendsAlistair Francis
Imply the TPM sysbus devices. This allows users to add TPM devices to the RISC-V virt board. This was tested by first creating an emulated TPM device: swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \ --ctrl type=unixio,path=swtpm-sock Then launching QEMU with: -chardev socket,id=chrtpm,path=swtpm-sock \ -tpmdev emulator,id=tpm0,chardev=chrtpm \ -device tpm-tis-device,tpmdev=tpm0 The TPM device can be seen in the memory tree and the generated device tree. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/942 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220427234146.1130752-7-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29hw/riscv: virt: Add device plug supportAlistair Francis
Add support for plugging in devices, this was tested with the TPM device. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220427234146.1130752-6-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29hw/riscv: virt: Add support for generating platform FDT entriesAlistair Francis
Similar to the ARM virt machine add support for adding device tree entries for dynamically created devices. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20220427234146.1130752-5-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29hw/riscv: virt: Create a platform busAlistair Francis
Create a platform bus to allow dynamic devices to be connected. This is based on the ARM implementation. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220427234146.1130752-4-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29hw/core: Move the ARM sysbus-fdt to coreAlistair Francis
The ARM virt machine currently uses sysbus-fdt to create device tree entries for dynamically created MMIO devices. The RISC-V virt machine can also benefit from this, so move the code to the core directory. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220427234146.1130752-3-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29hw/riscv: virt: Add a machine done notifierAlistair Francis
Move the binary and device tree loading code to the machine done notifier. This allows us to prepare for editing the device tree as part of the notifier. This is based on similar code in the ARM virt machine. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220427234146.1130752-2-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29hw/riscv: Don't add empty bootargs to device treeBin Meng
Commit 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree") tried to avoid adding *NULL* bootargs to device tree, but unfortunately the changes were entirely useless, due to MachineState::kernel_cmdline can't be NULL at all as the default value is given as an empty string. (see hw/core/machine.c::machine_initfn()). Note the wording of *NULL* bootargs is wrong. It can't be NULL otherwise a segfault had already been observed by dereferencing the NULL pointer. It should be worded as *empty" bootargs. Fixes: 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree") Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220421055629.1177285-2-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-29hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionallyBin Meng
At present the adding '/chosen/stdout-path' property in device tree is determined by whether a kernel command line is provided, which is wrong. It should be added unconditionally. Fixes: 8d8897accb1c ("hw/riscv: spike: Allow using binary firmware as bios") Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220421055629.1177285-1-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-28Merge tag 'pull-target-arm-20220428' of ↵Richard Henderson
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * refactor to use tcg_constant where appropriate * Advertise support for FEAT_TTL and FEAT_BBM level 2 * smmuv3: Cache event fault record * smmuv3: Add space in guest error message * smmuv3: Advertise support for SMMUv3.2-BBML2 # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmJqpu4ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3pOQD/9G190+ntJm4Vndz0I6bCDP # svDrWwsioOJ4q5Pah6517JACkwN5sx0adMGyAeRC3Kcbz5B2141vv9hJOnJmLB1D # l6KbH8XZaftC0B8fXsPkaH6XEdBHGz6YbOZaLOTwmFqF9d18OFW4d8+CAvfldZRc # +DYeolEhoL9eLTS16BlXPxb0LajQHhbN1Xdu3t8CGh31C52ZrG4h8cus6YMEDjfA # rfBthh/2QvVFmDedIfX4QrlImCTs+bTaSkhUBmX6qakWII0QykItgQTEZ8IHEr8/ # QmG+xlkP1MmffyHU3F4inEVXpjCSzula4ycZpNVGsrTHYxLBzsTSD+EzicLHMZSt # 64tQhLxPjAzC1MEHp7bJHyQXon7REWd6u1jPRlMWTGpZqbMMchBPjFrsxK3YPdvi # a/8KIulXuX+GjzbOIHnpttIy+U0UrjTEyxjpk+Ay2iZ+U6+hA3i2ni++dzq9dYb6 # IiCl+o29r/7fNaWpG3b38kn9vpxjwAAw+qfwwSqyM+8/KMirgJ8rpEmUPei/h7fy # vqpNlVxd1+Tzb3ljCXNRriZ05xo5I9LIb+dLAig1orENS7w3SzW/GnM+S7raOwQb # u9mxNmbQJ1MhkjNC/6wzniBre6EBs31X2GIWeuiWe/js2YFPQC06b1WwIc/bYNUv # anbECOS34mtxbExFfdlxUQ== # =IPEn # -----END PGP SIGNATURE----- # gpg: Signature made Thu 28 Apr 2022 07:38:38 AM PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] * tag 'pull-target-arm-20220428' of https://git.linaro.org/people/pmaydell/qemu-arm: (54 commits) hw/arm/smmuv3: Advertise support for SMMUv3.2-BBML2 target/arm: Advertise support for FEAT_BBM level 2 target/arm: Advertise support for FEAT_TTL hw/arm/smmuv3: Add space in guest error message hw/arm/smmuv3: Cache event fault record target/arm: Use field names for accessing DBGWCRn target/arm: Disable cryptographic instructions when neon is disabled target/arm: Use tcg_constant for vector descriptor target/arm: Use tcg_constant for do_brk{2,3} target/arm: Use tcg_constant for predicate descriptors target/arm: Use tcg_constant in do_zzi_{sat, ool}, do_fp_imm target/arm: Use tcg_constant in SUBR target/arm: Use tcg_constant in LD1, ST1 target/arm: Use tcg_constant in WHILE target/arm: Use tcg_constant in do_clast_scalar target/arm: Use tcg_constant in {incr, wrap}_last_active target/arm: Use tcg_constant in FCPY, CPY target/arm: Use tcg_constant in SINCDEC, INCDEC target/arm: Use tcg_constant for trans_INDEX_* target/arm: Use tcg_constant in trans_CSEL ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-04-28hw/arm/smmuv3: Advertise support for SMMUv3.2-BBML2Peter Maydell
The Arm SMMUv3 includes an optional feature equivalent to the CPU FEAT_BBM, which permits an OS to switch a range of memory between "covered by a huge page" and "covered by a sequence of normal pages" without having to engage in the traditional 'break-before-make' dance. (This is particularly important for the SMMU, because devices performing I/O through an SMMU are less likely to be able to cope with the window in the sequence where an access results in a translation fault.) The SMMU spec explicitly notes that one of the valid ways to be a BBM level 2 compliant implementation is: * if there are multiple entries in the TLB for an address, choose one of them and use it, ignoring the others Our SMMU TLB implementation (unlike our CPU TLB) does allow multiple TLB entries for an address, because the translation table level is part of the SMMUIOTLBKey, and so our IOTLB hashtable can include entries for the same address where the leaf was at different levels (i.e. both hugepage and normal page). Our TLB lookup implementation in smmu_iotlb_lookup() will always find the entry with the lowest level (i.e. it prefers the hugepage over the normal page) and ignore any others. TLB invalidation correctly removes all TLB entries matching the specified address or address range (unless the guest specifies the leaf level explicitly, in which case it gets what it asked for). So we can validly advertise support for BBML level 2. Note that we still can't yet advertise ourselves as an SMMU v3.2, because v3.2 requires support for the S2FWB feature, which we don't yet implement. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20220426160422.2353158-4-peter.maydell@linaro.org
2022-04-28hw/arm/smmuv3: Add space in guest error messageJean-Philippe Brucker
Make the translation error message prettier by adding a missing space before the parenthesis. Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20220427111543.124620-2-jean-philippe@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-04-28hw/arm/smmuv3: Cache event fault recordJean-Philippe Brucker
The Record bit in the Context Descriptor tells the SMMU to report fault events to the event queue. Since we don't cache the Record bit at the moment, access faults from a cached Context Descriptor are never reported. Store the Record bit in the cached SMMUTransCfg. Fixes: 9bde7f0674fe ("hw/arm/smmuv3: Implement translate callback") Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20220427111543.124620-1-jean-philippe@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-04-28meson: remove CONFIG_XEN_PCI_PASSTHROUGH from config-target.hPaolo Bonzini
CONFIG_XEN_PCI_PASSTHROUGH is just a global configuration option; it is never used in the source files, so there is no need to put CONFIG_XEN_PCI_PASSTHROUGH in config-target.h or even in config-host.h. This inaccuracy was copied over from the configure script in commit 8a19980e3f ("configure: move accelerator logic to meson", 2020-10-03). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-27Merge tag 'kraxel-20220427-pull-request' of git://git.kraxel.org/qemu into ↵Richard Henderson
staging vnc: add display-update monitor command. screendump: add png support. vmsvga: screen update fix. i386: sev setup for -bios loaded firmware # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEoDKM/7k6F6eZAf59TLbY7tPocTgFAmJpfYUACgkQTLbY7tPo # cTg6ChAAn5EWtNwmVbfbVzRTu0kqdx7QXyK6FFgTgXrsrmBCWzJhHDraYa9cMOZU # wBlU/Rutuv9ETvtRTRic3t0qcdRmvZjpHuA/3agBMJY7xpEQbQ8NwVdSRZTOZo0i # hXzWEAnxviEv8F/W1TXwB5d2Q9sWlJ2yO8SvcxTfAEK7hOSFrWypp3XRKr5WBHjO # DFTtwqTk9MRNsgsfnpEHNGDb30JPTqKZKRbDal15NDR9fQz+iCq3FIv/FpBaUfys # v9GA2zNT324MvhR64xNblaujCn2XFOsFvDY4nGDrfbKGJch8ltAg5t4G1CCZqOn7 # NIiwodC0508sAv9xUm+qvh+oHyf11EFdcAMWYimrExY2I51XOEDnJip/SAdogo5u # h7LyLkZTEG5tyc+a4PGIcC216ecDDNytMnJM9nh9YK3p5UiBOgcHV2wWDdzJbsdS # GRoP0fzF/MBQd985HBCF2vtQVk4AbQA7atZ8FKp1ZsHr3sFfs+vd0xyItsDMinBP # k/eKOOKbHRgXcdIocw4PK16yURrMo5IUGCGGiG9waqYz+VDyHhtikBAzQvYYdnqN # NaZttCcEieIk4XNd+wCfI0GQLtOY/AP1k8TV0rCaDTnO6nOxJ/uP64IaCzxzCT10 # b8VRdCfYDGjd2C14XYKmTzBRPM4hVrf9bo7FtXVtmSksTG+eIao= # =yaxh # -----END PGP SIGNATURE----- # gpg: Signature made Wed 27 Apr 2022 10:29:41 AM PDT # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [undefined] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [undefined] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * tag 'kraxel-20220427-pull-request' of git://git.kraxel.org/qemu: i386: firmware parsing and sev setup for -bios loaded firmware i386: factor out x86_firmware_configure() i386: move bios load error message avocado/vnc: add test_change_listen qapi/ui: add 'display-update' command for changing listen address ui/vnc: refactor arrays of addresses to SocketAddressList Added parameter to take screenshot with screendump as PNG Replacing CONFIG_VNC_PNG with CONFIG_PNG hw/display/vmware_vga: do not discard screen updates Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-04-27i386: firmware parsing and sev setup for -bios loaded firmwareGerd Hoffmann
Don't register firmware as rom, not needed (see comment). Add x86_firmware_configure() call for proper sev initialization. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Tested-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Tested-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20220425135051.551037-4-kraxel@redhat.com>
2022-04-27i386: factor out x86_firmware_configure()Gerd Hoffmann
move sev firmware setup to separate function so it can be used from other code paths. No functional change. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Tested-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20220425135051.551037-3-kraxel@redhat.com>
2022-04-27i386: move bios load error messageGerd Hoffmann
Switch to usual goto-end-of-function error handling style. No functional change. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Tested-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20220425135051.551037-2-kraxel@redhat.com>
2022-04-26Merge tag 'pull-nios2-20220426' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson
Fix nios2-linux-user syscalls. Fix nios2-linux-user sigreturn. Enable tests for nios2-linux-user. Remove special handling of SIGSEGV. Check supervisor for eret, bret. Split special registers out of env->regs[]. Clean up interrupt processing. Raise unaligned data and destination exceptions. Set TLBMISC fields correctly on exceptions. Prevent writes to read-only or reserved control fields. Use tcg_constant_tl(). Implement shadow register sets. Implement external interrupt controller interface. Implement vectored interrupt controller. Enable semihosting tests for nios2-softmmu. # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmJoNuQdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+a0ggAhawc3tod4OTHRlRq # rvZrJK740bNMo8rtidDnh71+IGjBiz8pXahqkE78cADtMzNmQoScwWbjht3cuMN2 # TMV0sbNDeA2OB98QzX6JTbCRtEfQAB7pyjpFvg6oXhYYSfwwhWbTR9QsYTHjq157 # ZKOprafoSlmDlgWJhlAikLdvJb07/5jgmvsLbBzu8/G/HiJ4HhHyjZxL1wNz1t/+ # 0KTAbnn3SWGDAhLGS/P6BMZKeU1EAExAwo7CtZeUbs+9QCfeM3cBAurG3WB1Vw14 # ERPoGPPrARtoNPtgQFMHu0am3HH5HtneuzJfWaLT96rrwNyTrYY0EYti1NtFDW8O # CCz42Q== # =MHar # -----END PGP SIGNATURE----- # gpg: Signature made Tue 26 Apr 2022 11:16:04 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-nios2-20220426' of https://gitlab.com/rth7680/qemu: (68 commits) tests/tcg/nios2: Add test-shadow-1 tests/tcg/nios2: Add semihosting multiarch tests hw/nios2: Machine with a Vectored Interrupt Controller hw/nios2: Move memory regions into Nios2Machine hw/nios2: Introduce Nios2MachineState hw/intc: Vectored Interrupt Controller (VIC) linux-user/nios2: Handle various SIGILL exceptions target/nios2: Advance pc when raising exceptions target/nios2: Implement EIC interrupt processing target/nios2: Update helper_eret for shadow registers target/nios2: Implement rdprs, wrprs target/nios2: Introduce shadow register sets target/nios2: Implement Misaligned destination exception target/nios2: Use tcg_gen_lookup_and_goto_ptr target/nios2: Use gen_goto_tb for DISAS_TOO_MANY target/nios2: Hoist set of is_jmp into gen_goto_tb target/nios2: Create gen_jumpr target/nios2: Enable unaligned traps for system mode target/nios2: Drop CR_STATUS_EH from tb->flags target/nios2: Introduce dest_gpr ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-04-26Merge tag 'misc-next-pull-request' of https://gitlab.com/berrange/qemu into ↵Richard Henderson
staging Misc patch queue * Removes depecated --enable-fips QEMU system emulator option * Fixes array bounds check in keycode conversion for ESCC device # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE2vOm/bJrYpEtDo4/vobrtBUQT98FAmJoDAoACgkQvobrtBUQ # T99iOg/+LeLLLKtjVx2HFzDgXWy9F5gGBzUNv4tqlkqDHMSdKWrMJAZfQXNMIeIN # NsIc7cJW9usZj9kPrLIMjXQziVaqFzuwGrD0A9ESJOEI/quPFuQ6clUL+Qs7leRz # SaoGHjprDy9TRe+e9B418LDIL29a2e5KUDa/HgpZJfXQRuSx93lutaNqm5MwGs8+ # WllO0fIi/6N2IJlaBwoYWZJ1VdV3DbokS/We9p2BAMCaxk16w/2o+W+drBkaxjaS # hihicW50JJgn4B7uUKqpHKRLkdmYatBcdqUc2aIuKZ6URx/cS6A0Oxt2coKhhOHV # vIDsUhqK03sfIPmQhr5HWeKpCs5lANgu0tmKIYZac5qIZFN/1ATpoKOZD8IZ1K25 # GOC7p7wDDTB6KaAqpCXDBZc7Kp4CbCYR79VciI1XNxFXiKgkqfaXRwr9JPM0oseo # QKLdb5Xn3c0HvjDKnEmO3BR5jx9E0QabK8WwplodCJJfpu349eUflNRdiH74iDFk # +AO4hShIr56Ksuj/GSWwIk4YeE0Ct2viZqjjIEGGWAKCQT1aultIH1pZcvCrTUVe # qyWSHx1lmqgOwGOF15xHo8yBZAa/o/SAv8V4FDVwXAzLU1eg144fJupkMMEMd3Og # PLnuR14Bii8K1pSkZbGSXqMxEybSmjnLlEh4xJxX0t/q4clzE0U= # =NiU1 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 26 Apr 2022 08:13:14 AM PDT # gpg: using RSA key DAF3A6FDB26B62912D0E8E3FBE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" [full] # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" [full] * tag 'misc-next-pull-request' of https://gitlab.com/berrange/qemu: github: fix config mistake preventing repo lockdown commenting hw/char: fix qcode array bounds check in ESCC impl softmmu: remove deprecated --enable-fips option Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-04-26hw/nios2: Machine with a Vectored Interrupt ControllerAmir Gonnen
Demonstrate how to use nios2 VIC on a machine. Introduce a new machine property to attach a VIC. When VIC is present, let the CPU know that it should use the External Interrupt Interface instead of the Internal Interrupt Interface. The devices on the machine are attached to the VIC and not directly to cpu. To allow VIC update EIC fields, we set the "cpu" property of the VIC with a reference to the nios2 cpu. [rth: Put a property on the 10m50-ghrd machine, rather than create a new machine class.] Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Amir Gonnen <amir.gonnen@neuroblade.ai> Message-Id: <20220303153906.2024748-6-amir.gonnen@neuroblade.ai> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-63-richard.henderson@linaro.org>
2022-04-26hw/nios2: Move memory regions into Nios2MachineRichard Henderson
Convert to contiguous allocation, as much as possible so far. The two timer objects are not exposed for subobject allocation. Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-62-richard.henderson@linaro.org>
2022-04-26hw/nios2: Introduce Nios2MachineStateRichard Henderson
We want to move data from the heap into Nios2MachineState, which is not possible with DEFINE_MACHINE. Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-61-richard.henderson@linaro.org>
2022-04-26hw/intc: Vectored Interrupt Controller (VIC)Amir Gonnen
Implement nios2 Vectored Interrupt Controller (VIC). VIC is connected to EIC. It needs to update rha, ril, rrs and rnmi fields on Nios2CPU before raising an IRQ. For that purpose, VIC has a "cpu" property which should refer to the nios2 cpu and set by the board that connects VIC. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Amir Gonnen <amir.gonnen@neuroblade.ai> Message-Id: <20220303153906.2024748-5-amir.gonnen@neuroblade.ai> [rth: Split out nios2_vic.h] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-60-richard.henderson@linaro.org>
2022-04-26hw/char: fix qcode array bounds check in ESCC implDaniel P. Berrangé
There was an off-by-1 in the qcode conversion array bounds check. Fixes: e709a61a8fe1076a487376fd657544418a38ba06 Reported-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2022-04-26vdpa: Add missing tracing to batch mapping functionsEugenio Pérez
These functions were not traced properly. Signed-off-by: Eugenio Pérez <eperezma@redhat.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20220405063628.853745-1-eperezma@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-04-26hw/pvrdma: Some cosmetic fixesYuval Shaia
Signed-off-by: Yuval Shaia <yuval.shaia.ml@gmail.com> Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <20220403095837.2378-1-yuval.shaia.ml@gmail.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-04-22Merge tag 'pull-target-arm-20220422-1' of ↵Richard Henderson
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Implement GICv4 emulation * Some cleanup patches in target/arm * hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate() # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmJisasZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3vcdEACIcvC8E93tFfeKwDQHSdPx # 7dPCdq+EZc/xEA2U/q282PFtvNBP6zo65RzWKXTkyfE5exLkCmqJqXSIUVfiuTyT # IAx9mL++StpBJMiqAebzEp2n8gwG7JymFeGuHYGet/nRrcwQYacBNxSl+BIVqZAm # mUy2UOlqJDlzMAVOcs/Ikfhj0z3qa52aZ8eF6sQI3mbSggiSIWOhyzNYo7jMB1x7 # UuHlYpvYDltKT7PveA5JSuBP9OmV5RrqqO4s5c22Y+o4k+La/NURDPdegblMfRA9 # MfWAEHqjA1WQaxh/Tb4Bex1u875mFMOXMZk3P910wSeqxMLhTCmjTA2g4p1KhfcA # LQJ5G2IvSA7HN660NLhZAqL601/1tS7Qcl387TfcU7WCDbgmzv2RCvH6UACF2hVl # CH4bC3lKvemT324aOBs/TCnvdu54qR6hkJZ57XSn59QHvrRvrREVdYNfQnl/g751 # GTp8aMcmvTkZ8I7k2t4Tx+CoFO38+rv7PupLN+Eq4k97ovXmAWxekizv8KYu5itY # emg63kItorwCgRwkKP28RKWLS/7dEpoF8sg5jBiBtGBGNG0AWPq4GZdrhaL58cr4 # lr4nSseN2IRsrp3SgM2203RjdghFM8ey1Dq+x2mRp+Q21vVTltI/VSiUSz0c2Vpo # JgbC4Jo+jufMkav31zOCAg== # =jqHX # -----END PGP SIGNATURE----- # gpg: Signature made Fri 22 Apr 2022 06:46:19 AM PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] * tag 'pull-target-arm-20220422-1' of https://git.linaro.org/people/pmaydell/qemu-arm: (61 commits) hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate() target/arm: Use tcg_constant_i32 in translate.h target/arm: Use tcg_constant in translate-vfp.c target/arm: Use smin/smax for do_sat_addsub_32 target/arm: Use tcg_constant in translate-neon.c target/arm: Use tcg_constant in translate-m-nocp.c target/arm: Simplify aa32 DISAS_WFI target/arm: Simplify gen_sar target/arm: Simplify GEN_SHIFT in translate.c target/arm: Split out gen_rebuild_hflags target/arm: Split out set_btype_raw target/arm: Remove fpexc32_access target/arm: Change CPUArchState.thumb to bool target/arm: Change DisasContext.thumb to bool target/arm: Extend store_cpu_offset to take field size target/arm: Change CPUArchState.aarch64 to bool target/arm: Change DisasContext.aarch64 to bool target/arm: Update SCTLR bits to ARMv9.2 target/arm: Update SCR_EL3 bits to ARMv8.8 target/arm: Update ISAR fields for ARMv8.8 ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-04-22hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in ↵Xiang Chen
smmuv3_translate() It always calls the IOMMU MR translate() callback with flag=IOMMU_NONE in memory_region_iommu_replay(). Currently, smmuv3_translate() return an IOMMUTLBEntry with perm set to IOMMU_NONE even if the translation success, whereas it is expected to return the actual permission set in the table entry. So pass the actual perm to returned IOMMUTLBEntry in the table entry. Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 1650094695-121918-1-git-send-email-chenxiang66@hisilicon.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-04-22hw/arm/virt: Support TCG GICv4Peter Maydell
Add support for the TCG GICv4 to the virt board. For the board, the GICv4 is very similar to the GICv3, with the only difference being the size of the redistributor frame. The changes here are thus: * calculating virt_redist_capacity correctly for GICv4 * changing various places which were "if GICv3" to be "if not GICv2" * the commandline option handling Note that using GICv4 reduces the maximum possible number of CPUs on the virt board from 512 to 317, because we can now only fit half as many redistributors into the redistributor regions we have defined. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-42-peter.maydell@linaro.org
2022-04-22hw/arm/virt: Abstract out calculation of redistributor region capacityPeter Maydell
In several places in virt.c we calculate the number of redistributors that fit in a region of our memory map, which is the size of the region divided by the size of a single redistributor frame. For GICv4, the redistributor frame is a different size from that for GICv3. Abstract out the calculation of redistributor region capacity so that we have one place we need to change to handle GICv4 rather than several. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-41-peter.maydell@linaro.org
2022-04-22hw/arm/virt: Use VIRT_GIC_VERSION_* enum values in create_gic()Peter Maydell
Everywhere we need to check which GIC version we're using, we look at vms->gic_version and use the VIRT_GIC_VERSION_* enum values, except in create_gic(), which copies vms->gic_version into a local 'int' variable and makes direct comparisons against values 2 and 3. For consistency, change this function to check the GIC version the same way we do elsewhere. This includes not implicitly relying on the enumeration type values happening to match the integer 'revision' values the GIC device object wants. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-40-peter.maydell@linaro.org
2022-04-22hw/intc/arm_gicv3: Allow 'revision' property to be set to 4Peter Maydell
Now that we have implemented all the GICv4 requirements, relax the error-checking on the GIC object's 'revision' property to allow a TCG GIC to be a GICv4, whilst still constraining the KVM GIC to GICv3. Our 'revision' property doesn't consider the possibility of wanting to specify the minor version of the GIC -- for instance there is a GICv3.1 which adds support for extended SPI and PPI ranges, among other things, and also GICv4.1. But since the QOM property is internal to QEMU, not user-facing, we can cross that bridge when we come to it. Within the GIC implementation itself code generally checks against the appropriate ID register feature bits, and the only use of s->revision is for setting those ID register bits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-39-peter.maydell@linaro.org
2022-04-22hw/intc/arm_gicv3: Update ID and feature registers for GICv4Peter Maydell
Update the various GIC ID and feature registers for GICv4: * PIDR2 [7:4] is the GIC architecture revision * GICD_TYPER.DVIS is 1 to indicate direct vLPI injection support * GICR_TYPER.VLPIS is 1 to indicate redistributor support for vLPIs * GITS_TYPER.VIRTUAL is 1 to indicate vLPI support * GITS_TYPER.VMOVP is 1 to indicate that our VMOVP implementation handles cross-ITS synchronization for the guest * ICH_VTR_EL2.nV4 is 0 to indicate direct vLPI injection support Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-38-peter.maydell@linaro.org
2022-04-22hw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi()Peter Maydell
Implement the function gicv3_redist_inv_vlpi(), which was previously left as a stub. This is the function that does the work of the INV command for a virtual interrupt. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-37-peter.maydell@linaro.org
2022-04-22hw/intc/arm_gicv3_redist: Implement gicv3_redist_vinvall()Peter Maydell
Implement the gicv3_redist_vinvall() function (previously left as a stub). This function handles the work of a VINVALL command: it must invalidate any cached information associated with a specific vCPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-36-peter.maydell@linaro.org
2022-04-22hw/intc/arm_gicv3_redist: Implement gicv3_redist_mov_vlpi()Peter Maydell
Implement the gicv3_redist_mov_vlpi() function (previously left as a stub). This function handles the work of a VMOVI command: it marks the vLPI not-pending on the source and pending on the destination. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-35-peter.maydell@linaro.org
2022-04-22hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov handlingPeter Maydell
We can use our new set_pending_table_bit() utility function in gicv3_redist_mov_lpi() to clear the bit in the source pending table, rather than doing the "load, clear bit, store" ourselves. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-34-peter.maydell@linaro.org
2022-04-22hw/intc/arm_gicv3_redist: Implement gicv3_redist_vlpi_pending()Peter Maydell
Implement the function gicv3_redist_vlpi_pending(), which was previously left as a stub. This is the function that is called by the CPU interface when it changes the state of a vLPI. It's similar to gicv3_redist_process_vlpi(), but we know that the vCPU is definitely resident on the redistributor and the irq is in range, so it is a bit simpler. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-33-peter.maydell@linaro.org
2022-04-22hw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi()Peter Maydell
Implement the function gicv3_redist_process_vlpi(), which was left as just a stub earlier. This function deals with being handed a VLPI by the ITS. It must set the bit in the pending table. If the vCPU is currently resident we must recalculate the highest priority pending vLPI; otherwise we may need to ring a "doorbell" interrupt to let the hypervisor know it might want to reschedule the vCPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-32-peter.maydell@linaro.org
2022-04-22hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" codePeter Maydell
Factor out the code which sets a single bit in an LPI pending table. We're going to need this for handling vLPI tables, not just the physical LPI table. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-31-peter.maydell@linaro.org
2022-04-22hw/intc/arm_gicv3_redist: Recalculate hppvlpi on VPENDBASER writesPeter Maydell
The guest uses GICR_VPENDBASER to tell the redistributor when it is scheduling or descheduling a vCPU. When it writes and changes the VALID bit from 0 to 1, it is scheduling a vCPU, and we must update our view of the current highest priority pending vLPI from the new Pending and Configuration tables. When it writes and changes the VALID bit from 1 to 0, it is descheduling, which means that there is no longer a highest priority pending vLPI. The specification allows the implementation to use part of the vLPI Pending table as an IMPDEF area where it can cache information when a vCPU is descheduled, so that it can avoid having to do a full rescan of the tables when the vCPU is scheduled again. For now, we don't take advantage of this, and simply do a complete rescan. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-30-peter.maydell@linaro.org
2022-04-22hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all LPIs" logicPeter Maydell
Factor out the common part of gicv3_redist_update_lpi_only() into a new function update_for_all_lpis(), which does a full rescan of an LPI Pending table and sets the specified PendingIrq struct with the highest priority pending enabled LPI it finds. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-29-peter.maydell@linaro.org
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-25 05:40:29 +0000