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2011-10-06PPC: Enable to use PAPR with PR style KVMAlexander Graf
When running PR style KVM, we need to tell the kernel that we want to run in PAPR mode now. This means that we need to pass some more register information down and enable papr mode. We also need to align the HTAB to htab_size boundary. Using this patch, -M pseries works with kvm even on non-hv kvm implementations, as long as the preceding kernel patches are in. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - match on CONFIG_PSERIES v2 -> v3: - remove HIOR pieces from PAPR patch (ABI breakage)
2011-10-06PPC: E500: Bump CPU count to 15Alexander Graf
Now that we have everything in place, make the machine description aware of the fact that we can now handle 15 virtual CPUs! Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - Max cpus is 15 because of MPIC
2011-10-06MPC8544DS: Generate CPU nodes on initAlexander Graf
With this patch, we generate CPU nodes in the machine initialization, giving us the freedom to generate as many nodes as we want and as the machine supports, but only those. This is a first step towards a much cleaner device tree generation infrastructure, where we would not require precompiled dtb blobs anymore. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: Update cpu-release-addr property in cpu nodesAlexander Graf
The guest OS wants to know where the guest spins, so let's tell him while updating the CPU nodes with the frequencies anyways. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - use new spin table address
2011-10-06PPC: E500: Add PV spinning codeAlexander Graf
CPUs that are not the boot CPU need to run in spinning code to check if they should run off to execute and if so where to jump to. This usually happens by leaving secondary CPUs looping and checking if some variable in memory changed. In an environment like Qemu however we can be more clever. We can just export the spin table the primary CPU modifies as MMIO region that would event based wake up the respective secondary CPUs. That saves us quite some cycles while the secondary CPUs are not up yet. So this patch adds a PV device that simply exports the spinning table into the guest and thus allows the primary CPU to wake up secondary ones. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - change into MMIO scheme - map the secondary NIP instead of 0 1:1 - only map 64MB for TLB, same as u-boot - prepare code for 64-bit spinnings v2 -> v3: - remove r6 - set MAS2_M - map EA 0 - use second TLB1 entry v3 -> v4: - change to memoryops v4 -> v5: - fix endianness bugs v5 -> v6: - add header
2011-10-06PPC: E500: Remove unneeded CPU nodesAlexander Graf
We should only keep CPU nodes in the device tree around that we really have virtual CPUs for. So remove all superfluous entries that we just keep there in case someone wants to create a lot of vCPUs. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: Update freqs for all CPUsAlexander Graf
Now that we can so nicely find out the host's frequencies, we should also make sure that we get them into all virtual CPUs' device tree nodes. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: bamboo: Use kvm api for freq and clock frequenciesAlexander Graf
Now that we have nice and shiny APIs to read out the host's clock and timebase frequencies, let's use them in the bamboo code as well! Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: Remove mpc8544_copy_soc_cellAlexander Graf
We don't need mpc8544_copy_soc_cell anymore, since we're explicitly reading host values and writing guest values respectively. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: Use generic kvm function for freqAlexander Graf
Now that we have generic KVM functions to read out the host tb and clock frequencies, let's use them in the e500 code! Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: bamboo: Move host fdt copy to targetAlexander Graf
We have some code in generic kvm_ppc.c that is only used by 440. Move to the 440 specific device code. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: Generate IRQ lines for many CPUsAlexander Graf
Now that we can generate multiple envs for all our virtual CPUs, we also need to tell the MPIC that we have multiple CPUs connected and connect them all to the respective virtual interrupt lines. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: create multiple envsAlexander Graf
When creating a VM, we should go through smp_cpus and create a virtual CPU for every CPU the user requested. This patch adds support for that and moves some code around to make that more convenient. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: Bump MPIC up to 32 supported CPUsAlexander Graf
The MPIC emulation is now capable of handling up to 32 CPUs. Reflect that in the code exporting the numbers out and fix an integer overflow while at it. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - Max cpus is 15 due to cINT routing - Report nb_cpus not MAX_CPUS in MPIC capabilities
2011-10-06PPC: MPIC: Fix CI bit definitionsAlexander Graf
The bit definitions for critical interrupt routing are in PowerPC order (most significant bit is 0), while we end up shifting it with normal bit order. Turn the numbers around so we actually end up fetching the right ones. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: MPIC: Remove read functionality for WO registersAlexander Graf
The IPI dispatch registers are write only according to every MPIC spec I have found. So instead of pretending you could read back something from them, better not handle them at all. Reported-by: Elie Richa <richa@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: Set MPIC IDE for IPI to 0Alexander Graf
We use the IDE register with IPIs as a mask to keep track which processors have already acknowledged the respective interrupt. So we need to initialize it to 0 to make sure that it doesn't accidently fire an IPI on CPU0 when the first IPI is triggered. Reported-by: Elie Richa <richa@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de> --- v2 -> v3: - fix IDE IPI reset
2011-10-06PPC: Fix IPI support in MPICAlexander Graf
The current IPI support in the MPIC code is incomplete and doesn't work. This code adds proper support for IPIs in MPIC by using the IDE register to remember which CPUs IPIs are still outstanding to. New triggers through the IPI trigger register only add to the list of CPUs we want to IPI. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - Use MAX_IPI instead of hardcoded 4 Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: Extend MPIC MMIO rangeAlexander Graf
The MPIC exports a page for each CPU that it controls. To support more than one CPU, we need to also reserve the MMIO space according to the amount of CPUs we want to support. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: Add CPU local MMIO regions to MPICAlexander Graf
The MPIC exports a register set for each CPU connected to it. They can all be accessed through specific registers or using a shadow page that is mapped differently depending on which CPU accesses it. This patch implements the shadow map, making it possible for guests to access the CPU local registers using the same address on each CPU. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06spapr: make irq customizable via qdevPaolo Bonzini
This also lets the user see the irq in "info qtree". Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Cc: Alexander Graf <agraf@suse.de> Cc: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06spapr: prepare for qdevification of irqPaolo Bonzini
Restructure common properties for sPAPR devices so that IRQ definitions can be added in one place. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Cc: Alexander Graf <agraf@suse.de> Cc: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06spapr: proper qdevificationPaolo Bonzini
Right now the spapr devices cannot be instantiated with -device, because the IRQs need to be passed to the spapr_*_create functions. Do this instead in the bus's init wrapper. This is particularly important with the conversion from scsi-disk to scsi-{cd,hd} that Markus made. After his patches, if you specify a scsi-cd device attached to an if=none drive, the default VSCSI controller will not be created and, without qdevification, you will not be able to add yours. NOTE from agraf: added small compile fix Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Cc: Alexander Graf <agraf@suse.de> Cc: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-03etrax-dma: Remove bogus if statementEdgar E. Iglesias
Reported-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-10-01ESP: convert to trace frameworkBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01PPC: Drop initial ESCC mappingAlexander Graf
We are mapping ESCC to a static (incorrect) address on machine init. This overlaps with our vram, rendering the screen barely usable. Since openBIOS is clever enough to map ESCC to where it needs to be, we can just drop that invalid map and everyone's happy. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01mips_fulong2e: Reorder ISA bus and i8259 creationJan Kiszka
Missed during memory region conversion: The i8259 now depends on the ISA bus being created first. Reorder the initialization. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-29Merge remote-tracking branch 'aneesh/for-upstream-5' into stagingAnthony Liguori
2011-09-27PPC: use memory API to construct the PCI holeBlue Swirl
Avoid vga.chain4 mapping by constructing a PCI hole for upper 2G of the PCI space. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-26Merge remote-tracking branch 'qemu-kvm-tmp/memory/urgent' into stagingAnthony Liguori
2011-09-26Merge remote-tracking branch 'qemu-kvm-tmp/memory/batch' into stagingAnthony Liguori
2011-09-26Merge remote-tracking branch 'pmaydell/omap-for-upstream' into stagingAnthony Liguori
2011-09-25ppc_prep: fix pci config space initializationAvi Kivity
Use data_mem for the data mmio region, not conf_mem. Signed-off-by: Avi Kivity <avi@redhat.com>
2011-09-25fdc: Convert isabus_fdc_init1 to MemoryRegionRichard Henderson
This requires some amount of hoop-jumping, so that we don't inadvertently claim port 0x3f6, which is used by ISA IDE. The sysbus initialization path is as yet unconverted. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-09-25serial: Convert serial_isa_initfn to MemoryRegionRichard Henderson
The serial_mm_init path is as yet unconverted. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-09-25pckbd: Convert to MemoryRegionRichard Henderson
Slightly non-obvious with mips_jazz passing in the region structure to populate. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-09-25i8259: Convert to MemoryRegionRichard Henderson
The only non-obvious part is pic_poll_read which used "addr1 >> 7" to detect whether one referred to either the master or slave PIC. Instead, test this directly. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-09-25ppc_prep: initialize i8259 after the ISA busAvi Kivity
Succeeding i8259 conversion to ISA requires this. Signed-off-by: Avi Kivity <avi@redhat.com>
2011-09-25mips_r4k: initialize i8259 after the ISA busAvi Kivity
Succeeding i8259 conversion to ISA requires this. Signed-off-by: Avi Kivity <avi@redhat.com>
2011-09-25mips_jazz: initialize i8259 after the ISA busAvi Kivity
Succeeding i8259 conversion to ISA requires this. Signed-off-by: Avi Kivity <avi@redhat.com>
2011-09-25mips_malta: move i8259 initialization after piix4 initializationAvi Kivity
i8259 is an ISA device (or at least, depends on the ISA infrastructure to register its ioport); and the ISA bus is supplied by piix4. Later patches make this dependency explicit. Use qemu_irq_proxy() to stop the cycle by adding an extra layer of indirection. Signed-off-by: Avi Kivity <avi@redhat.com>
2011-09-25i8254: Convert to MemoryRegionRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-09-25cs4231a: Convert to MemoryRegionRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-09-25pc: Re-order pc_init1 to initialize the ISA bus before ISA devicesRichard Henderson
In particular, the i8259 was being initialized before the ISA bus, leading to a crash. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-09-25isa: add isa_register_ioport()Richard Henderson
To replace isa_init_ioport and isa_init_ioport_range as the ISA devices are converted to the memory api. [avi: use memory_region_size()] Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-09-25isa: Pass i/o address space to isa_bus_newRichard Henderson
Not used yet, but at least we're provided with the correct region. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-09-25pci: add pci_address_space_io()Richard Henderson
Returns the I/O address space. Useful for implementing PCI-ISA bridge devices. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-09-23adlib: remove write-only variableHervé Poussineau
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-09-23irq: introduce qemu_irq_proxy()Avi Kivity
In some cases we have a circular dependency involving irqs - the irq controller depends on a bus, which in turn depends on the irq controller. Add qemu_irq_proxy() which acts as a passthrough, except that the target irq may be set later on. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-09-23virtio: Use global memory barrier macrosDavid Gibson
The virtio code uses wmb() macros in several places, as required by the SMP-aware virtio protocol. However the wmb() macro is locally defined to be a compiler barrier only. This is probably sufficient on x86 due to its strong storage ordering model, but it certainly isn't on other platforms, such as ppc. In any case, qemu already has some globally defined memory barrier macros in qemu-barrier.h. This patch, therefore converts virtio.c to use those barrier macros. The macros in qemu-barrier.h are also wrong (or at least, safe for x86 only) but this way at least there's only one place to fix them. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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