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2011-10-06PPC: E500: Bump CPU count to 15Alexander Graf
Now that we have everything in place, make the machine description aware of the fact that we can now handle 15 virtual CPUs! Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - Max cpus is 15 because of MPIC
2011-10-06MPC8544DS: Generate CPU nodes on initAlexander Graf
With this patch, we generate CPU nodes in the machine initialization, giving us the freedom to generate as many nodes as we want and as the machine supports, but only those. This is a first step towards a much cleaner device tree generation infrastructure, where we would not require precompiled dtb blobs anymore. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: Update cpu-release-addr property in cpu nodesAlexander Graf
The guest OS wants to know where the guest spins, so let's tell him while updating the CPU nodes with the frequencies anyways. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - use new spin table address
2011-10-06PPC: E500: Add PV spinning codeAlexander Graf
CPUs that are not the boot CPU need to run in spinning code to check if they should run off to execute and if so where to jump to. This usually happens by leaving secondary CPUs looping and checking if some variable in memory changed. In an environment like Qemu however we can be more clever. We can just export the spin table the primary CPU modifies as MMIO region that would event based wake up the respective secondary CPUs. That saves us quite some cycles while the secondary CPUs are not up yet. So this patch adds a PV device that simply exports the spinning table into the guest and thus allows the primary CPU to wake up secondary ones. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - change into MMIO scheme - map the secondary NIP instead of 0 1:1 - only map 64MB for TLB, same as u-boot - prepare code for 64-bit spinnings v2 -> v3: - remove r6 - set MAS2_M - map EA 0 - use second TLB1 entry v3 -> v4: - change to memoryops v4 -> v5: - fix endianness bugs v5 -> v6: - add header
2011-10-06PPC: E500: Remove unneeded CPU nodesAlexander Graf
We should only keep CPU nodes in the device tree around that we really have virtual CPUs for. So remove all superfluous entries that we just keep there in case someone wants to create a lot of vCPUs. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: Update freqs for all CPUsAlexander Graf
Now that we can so nicely find out the host's frequencies, we should also make sure that we get them into all virtual CPUs' device tree nodes. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: bamboo: Use kvm api for freq and clock frequenciesAlexander Graf
Now that we have nice and shiny APIs to read out the host's clock and timebase frequencies, let's use them in the bamboo code as well! Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: Remove mpc8544_copy_soc_cellAlexander Graf
We don't need mpc8544_copy_soc_cell anymore, since we're explicitly reading host values and writing guest values respectively. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: Use generic kvm function for freqAlexander Graf
Now that we have generic KVM functions to read out the host tb and clock frequencies, let's use them in the e500 code! Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: bamboo: Move host fdt copy to targetAlexander Graf
We have some code in generic kvm_ppc.c that is only used by 440. Move to the 440 specific device code. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: Generate IRQ lines for many CPUsAlexander Graf
Now that we can generate multiple envs for all our virtual CPUs, we also need to tell the MPIC that we have multiple CPUs connected and connect them all to the respective virtual interrupt lines. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: create multiple envsAlexander Graf
When creating a VM, we should go through smp_cpus and create a virtual CPU for every CPU the user requested. This patch adds support for that and moves some code around to make that more convenient. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: Bump MPIC up to 32 supported CPUsAlexander Graf
The MPIC emulation is now capable of handling up to 32 CPUs. Reflect that in the code exporting the numbers out and fix an integer overflow while at it. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - Max cpus is 15 due to cINT routing - Report nb_cpus not MAX_CPUS in MPIC capabilities
2011-10-06PPC: MPIC: Fix CI bit definitionsAlexander Graf
The bit definitions for critical interrupt routing are in PowerPC order (most significant bit is 0), while we end up shifting it with normal bit order. Turn the numbers around so we actually end up fetching the right ones. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: MPIC: Remove read functionality for WO registersAlexander Graf
The IPI dispatch registers are write only according to every MPIC spec I have found. So instead of pretending you could read back something from them, better not handle them at all. Reported-by: Elie Richa <richa@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: Set MPIC IDE for IPI to 0Alexander Graf
We use the IDE register with IPIs as a mask to keep track which processors have already acknowledged the respective interrupt. So we need to initialize it to 0 to make sure that it doesn't accidently fire an IPI on CPU0 when the first IPI is triggered. Reported-by: Elie Richa <richa@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de> --- v2 -> v3: - fix IDE IPI reset
2011-10-06PPC: Fix IPI support in MPICAlexander Graf
The current IPI support in the MPIC code is incomplete and doesn't work. This code adds proper support for IPIs in MPIC by using the IDE register to remember which CPUs IPIs are still outstanding to. New triggers through the IPI trigger register only add to the list of CPUs we want to IPI. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - Use MAX_IPI instead of hardcoded 4 Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: Extend MPIC MMIO rangeAlexander Graf
The MPIC exports a page for each CPU that it controls. To support more than one CPU, we need to also reserve the MMIO space according to the amount of CPUs we want to support. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: Add CPU local MMIO regions to MPICAlexander Graf
The MPIC exports a register set for each CPU connected to it. They can all be accessed through specific registers or using a shadow page that is mapped differently depending on which CPU accesses it. This patch implements the shadow map, making it possible for guests to access the CPU local registers using the same address on each CPU. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06spapr: make irq customizable via qdevPaolo Bonzini
This also lets the user see the irq in "info qtree". Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Cc: Alexander Graf <agraf@suse.de> Cc: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06spapr: prepare for qdevification of irqPaolo Bonzini
Restructure common properties for sPAPR devices so that IRQ definitions can be added in one place. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Cc: Alexander Graf <agraf@suse.de> Cc: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06spapr: proper qdevificationPaolo Bonzini
Right now the spapr devices cannot be instantiated with -device, because the IRQs need to be passed to the spapr_*_create functions. Do this instead in the bus's init wrapper. This is particularly important with the conversion from scsi-disk to scsi-{cd,hd} that Markus made. After his patches, if you specify a scsi-cd device attached to an if=none drive, the default VSCSI controller will not be created and, without qdevification, you will not be able to add yours. NOTE from agraf: added small compile fix Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Cc: Alexander Graf <agraf@suse.de> Cc: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-05lsi: Fix tag reference in debug printJan Kiszka
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-10-05gt64xxx.c: remove reference to non-existing ISD_handle fieldAntony Pavlov
The commit fc2bf44972349b078d8310466c3866615500e67f removed ISD_handle field from struct GT64120State, so remove the field from DPRINTF too. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-10-05gt64xxx.c: fix length modifier in DPRINTF format stringAntony Pavlov
The commit fc2bf44972349b078d8310466c3866615500e67f changed the type of val argument of the function gt64120_writel() from uint32_t to uint64_t, so we need to change the corresponding length modifier from "%x" to "%" PRIx64. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-10-04RunState: Rename enum values as generated by the QAPILuiz Capitulino
Next commit will convert the query-status command to use the RunState type as generated by the QAPI. In order to "transparently" replace the current enum by the QAPI one, we have to make some changes to some enum values. As the changes are simple renames, I'll do them in one shot. The changes are: - Rename the prefix from RSTATE_ to RUN_STATE_ - RUN_STATE_SAVEVM to RUN_STATE_SAVE_VM - RUN_STATE_IN_MIGRATE to RUN_STATE_INMIGRATE - RUN_STATE_PANICKED to RUN_STATE_INTERNAL_ERROR - RUN_STATE_POST_MIGRATE to RUN_STATE_POSTMIGRATE - RUN_STATE_PRE_LAUNCH to RUN_STATE_PRELAUNCH - RUN_STATE_PRE_MIGRATE to RUN_STATE_PREMIGRATE - RUN_STATE_RESTORE to RUN_STATE_RESTORE_VM - RUN_STATE_PRE_MIGRATE to RUN_STATE_FINISH_MIGRATE Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
2011-10-03milkymist: new interrupt mapMichael Walle
Due to the new uart core version the interrupt mapping has changed. Signed-off-by: Michael Walle <michael@walle.cc>
2011-10-03milkymist_uart: support new core versionMichael Walle
The new version of the uart core introduces status and control bits. Signed-off-by: Michael Walle <michael@walle.cc>
2011-10-03etrax-dma: Remove bogus if statementEdgar E. Iglesias
Reported-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-10-02milkymist-{minimac2,softusb}: rename memory namesMichael Walle
Be consistent with other milkymist models. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02milkymist-vgafb: convert to memory APIMichael Walle
Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02milkymist-uart: convert to memory APIMichael Walle
Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02milkymist-tmu2: convert to memory APIMichael Walle
Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02milkymist-sysctl: convert to memory APIMichael Walle
Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02milkymist-pfpu: convert to memory APIMichael Walle
Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02milkymist-memcard: convert to memory APIMichael Walle
Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02milkymist-hpdmc: convert to memory APIMichael Walle
Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02milkymist-ac97: convert to memory APIMichael Walle
Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02openpic: Memory API conversion for mpicFabien Chouteau
This patch converts mpic to the new memory API (through old mmio). Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02hw/smc91c111: Convert to MemoryRegionPeter Maydell
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02sun4u: Pass address_space_mem to sun4uv_initRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02sm501: Pass address_space_mem to sm501_initRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02pxa: Pass in address_space to pxa{255, 270}_initRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02ppc440: Pass in address_space_mem to ppc440ep_initRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02ppc405: Pass in address_space_mem to ppc405{cr, ep}_initRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02serial: Add MemoryRegion parameter to serial_mm_initRichard Henderson
Remove the get_system_memory() call from serial_mm_init, pushing it back into the callers. In many cases we already have the system memory region available. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02serial: Remove ioregister parameter from serial_mm_initRichard Henderson
All callers passed 1. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02serial: Use enum device_endian in serial_mm_init parameterRichard Henderson
The use of DEVICE_NATIVE_ENDIAN cleans up lots of ifdefs in many of the callers. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02serial: Convert serial_mm_init to MemoryRegionRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-10-02etrax-eth: Convert to MemoryRegionEdgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Avi Kivity <avi@redhat.com>
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