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2020-09-18Use OBJECT_DECLARE_SIMPLE_TYPE when possibleEduardo Habkost
This converts existing DECLARE_INSTANCE_CHECKER usage to OBJECT_DECLARE_SIMPLE_TYPE when possible. $ ./scripts/codeconverter/converter.py -i \ --pattern=AddObjectDeclareSimpleType $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Paul Durrant <paul@xen.org> Message-Id: <20200916182519.415636-6-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-18Use OBJECT_DECLARE_TYPE when possibleEduardo Habkost
This converts existing DECLARE_OBJ_CHECKERS usage to OBJECT_DECLARE_TYPE when possible. $ ./scripts/codeconverter/converter.py -i \ --pattern=AddObjectDeclareType $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Acked-by: Paul Durrant <paul@xen.org> Message-Id: <20200916182519.415636-5-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-18qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost
One of the goals of having less boilerplate on QOM declarations is to avoid human error. Requiring an extra argument that is never used is an opportunity for mistakes. Remove the unused argument from OBJECT_DECLARE_TYPE and OBJECT_DECLARE_SIMPLE_TYPE. Coccinelle patch used to convert all users of the macros: @@ declarer name OBJECT_DECLARE_TYPE; identifier InstanceType, ClassType, lowercase, UPPERCASE; @@ OBJECT_DECLARE_TYPE(InstanceType, ClassType, - lowercase, UPPERCASE); @@ declarer name OBJECT_DECLARE_SIMPLE_TYPE; identifier InstanceType, lowercase, UPPERCASE; @@ OBJECT_DECLARE_SIMPLE_TYPE(InstanceType, - lowercase, UPPERCASE); Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Acked-by: Cornelia Huck <cohuck@redhat.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Paul Durrant <paul@xen.org> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20200916182519.415636-4-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-18sifive: Use DECLARE_*CHECKER* macrosEduardo Habkost
$ ./scripts/codeconverter/converter.py -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20200831210740.126168-12-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-18sifive: Move QOM typedefs and add missing includesEduardo Habkost
Some typedefs and macros are defined after the type check macros. This makes it difficult to automatically replace their definitions with OBJECT_DECLARE_TYPE. Patch generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]') which will split "typdef struct { ... } TypedefName" declarations. Followed by: $ ./scripts/codeconverter/converter.py -i --pattern=MoveSymbols \ $(git grep -l '' -- '*.[ch]') which will: - move the typedefs and #defines above the type check macros - add missing #include "qom/object.h" lines if necessary Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20200831210740.126168-9-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-18sifive_u: Rename memmap enum constantsEduardo Habkost
Some of the enum constant names conflict with the QOM type check macros (SIFIVE_U_OTP, SIFIVE_U_PRCI). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to SIFIVE_U_DEV_*, to avoid conflicts. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200911173447.165713-3-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-18sifive_e: Rename memmap enum constantsEduardo Habkost
Some of the enum constant names conflict with a QOM type check macro (SIFIVE_E_PRCI). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to SIFIVE_E_DEV_*, to avoid conflicts. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200911173447.165713-2-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-18hw/nvram/fw_cfg: fix FWCfgDataGeneratorClass::get_data() consumptionLaszlo Ersek
The documentation on g_byte_array_free() <https://developer.gnome.org/glib/stable/glib-Byte-Arrays.html#g-byte-array-free> says: > Returns > > the element data if free_segment is FALSE, otherwise NULL. The element > data should be freed using g_free(). Because we currently call g_byte_array_free() with free_segment=TRUE, we end up passing data=NULL to fw_cfg_add_file(). On the plus side, fw_cfg_data_read() and fw_cfg_dma_transfer() both deal with NULL data gracefully: QEMU does not crash when the guest reads such an item, the guest just gets a properly sized, but zero-filled blob. However, the bug breaks UEFI HTTPS boot, as the IANA_TLS_CIPHER array, generated otherwise correctly by the "tls-cipher-suites" object, is in effect replaced with a zero blob. Fix the issue by passing free_segment=FALSE to g_byte_array_free(): - the caller (fw_cfg_add_from_generator()) temporarily assumes ownership of the generated byte array, - then ownership of the byte array is transfered to fw_cfg, as fw_cfg_add_file() links (not copies) "data" into fw_cfg. Cc: "Daniel P. Berrangé" <berrange@redhat.com> Cc: "Philippe Mathieu-Daudé" <philmd@redhat.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Fixes: 3203148917d035b09f71986ac2eaa19a352d6d9d Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20200916151510.22767-1-lersek@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2020-09-18Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20200918' ↵Peter Maydell
into staging Aspeed patches : * Couple of cleanups * New machine properties to define the flash models # gpg: Signature made Fri 18 Sep 2020 08:23:19 BST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-aspeed-20200918: misc: aspeed_scu: Update AST2600 silicon id register hw/arm/aspeed: Add machine properties to define the flash models hw/arm/aspeed: Map the UART5 device unconditionally Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-18misc: aspeed_scu: Update AST2600 silicon id registerJoel Stanley
Aspeed have released an updated datasheet (v7) containing the silicon id for the AST2600 A2. It looks like this: SCU004 SCU014 AST2600-A0 0x05000303 0x05000303 AST2600-A1 0x05010303 0x05010303 AST2600-A2 0x05010303 0x05020303 AST2620-A1 0x05010203 0x05010203 AST2620-A2 0x05010203 0x05020203 The SCU004 (silicon id 1) value matches SCU014 for A0, but for subsequent revisions it is hard coded to the A1 value. Qemu effectively dropped support for the A0 in 7582591ae745 ("aspeed: Support AST2600A1 silicon revision") as the A0 reset table was removed, so it makes sense to only support the behaviour of A1 and onwards. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200916082012.776628-1-joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2020-09-18hw/arm/aspeed: Add machine properties to define the flash modelsCédric Le Goater
Some machines don't have much differences a part from the flash model being used. Introduce new machine properties to change them from the command line. For instance, to start the ast2500-evb machine with a different FMC chip and a 64M SPI chip, use : -M ast2500-evb,fmc-model=mx25l25635e,spi-model=mx66u51235f Cc: 郁雷 <yulei.sh@bytedance.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Lei YU <yulei.sh@bytedance.com> Message-Id: <20200915054859.2338477-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2020-09-18hw/arm/aspeed: Map the UART5 device unconditionallyPhilippe Mathieu-Daudé
The UART5 is present on the machine regardless there is a character device connected to it. Map it unconditionally. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200905212415.760452-1-f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2020-09-17Merge remote-tracking branch ↵Peter Maydell
'remotes/kraxel/tags/microvm-20200917-pull-request' into staging microvm: add acpi support # gpg: Signature made Thu 17 Sep 2020 14:53:06 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/microvm-20200917-pull-request: (21 commits) microvm: enable ramfb tests/acpi: update expected data files for microvm tests/acpi: add microvm test tests/acpi: allow override blkdev tests/acpi: allow microvm test data updates. microvm: wire up hotplug x86: move cpu hotplug from pc to x86 x86: move acpi_dev from pc/microvm x86: constify x86_machine_is_*_enabled microvm/acpi: disable virtio-mmio cmdline hack microvm/acpi: use seabios with acpi=on microvm/acpi: use GSI 16-23 for virtio microvm/acpi: add acpi_dsdt_add_virtio() for x86 microvm/acpi: add minimal acpi support microvm: make virtio irq base runtime configurable acpi: move acpi_dsdt_add_power_button() to ged acpi: ged: add x86 device variant. acpi: ged: add control regs seabios: add bios-microvm.bin binary seabios: add microvm config, update build rules ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-17microvm: enable ramfbGerd Hoffmann
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20200915120909.20838-22-kraxel@redhat.com
2020-09-17microvm: wire up hotplugGerd Hoffmann
The cpu hotplug code handles the initialization of coldplugged cpus too, so it is needed even in case cpu hotplug is not supported. Wire cpu hotplug up for microvm. Without this we get a broken MADT table. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20200915120909.20838-17-kraxel@redhat.com
2020-09-17x86: move cpu hotplug from pc to x86Gerd Hoffmann
The cpu hotplug code handles the initialization of coldplugged cpus too, so it is needed even in case cpu hotplug is not supported. Move the code from pc to x86, so microvm can use it. Move both plug and unplug to keep everything in one place, even though microvm needs plug only. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20200915120909.20838-16-kraxel@redhat.com
2020-09-17x86: move acpi_dev from pc/microvmGerd Hoffmann
Both pc and microvm machine types have a acpi_dev field. Move it to the common base type. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20200915120909.20838-15-kraxel@redhat.com
2020-09-17x86: constify x86_machine_is_*_enabledGerd Hoffmann
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200915120909.20838-14-kraxel@redhat.com
2020-09-17microvm/acpi: disable virtio-mmio cmdline hackGerd Hoffmann
... in case we are using ACPI. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20200915120909.20838-13-kraxel@redhat.com
2020-09-17microvm/acpi: use seabios with acpi=onGerd Hoffmann
With acpi=off continue to use qboot. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20200915120909.20838-12-kraxel@redhat.com
2020-09-17microvm/acpi: use GSI 16-23 for virtioGerd Hoffmann
With ACPI enabled and IO-APIC being properly declared in the ACPI tables we can use interrupt lines 16-23 for virtio and avoid shared interrupts. With acpi disabled we continue to use lines 5-12. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20200915120909.20838-11-kraxel@redhat.com
2020-09-17microvm/acpi: add acpi_dsdt_add_virtio() for x86Gerd Hoffmann
Makes x86 linux kernel find virtio-mmio devices automatically. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20200915120909.20838-10-kraxel@redhat.com
2020-09-17microvm/acpi: add minimal acpi supportGerd Hoffmann
$subject says all. Can be controlled using -M microvm,acpi=on/off. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20200915120909.20838-9-kraxel@redhat.com
2020-09-17microvm: make virtio irq base runtime configurableGerd Hoffmann
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20200915120909.20838-8-kraxel@redhat.com
2020-09-17acpi: move acpi_dsdt_add_power_button() to gedGerd Hoffmann
Allow reuse for microvm. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20200915120909.20838-7-kraxel@redhat.com
2020-09-17acpi: ged: add x86 device variant.Gerd Hoffmann
Set AcpiDeviceIfClass->madt_cpu, otherwise identical to TYPE_ACPI_GED. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20200915120909.20838-6-kraxel@redhat.com
2020-09-17acpi: ged: add control regsGerd Hoffmann
Add control regs (sleep, reset) for hw-reduced acpi. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20200915120909.20838-5-kraxel@redhat.com
2020-09-17microvm: name qboot binary qboot.romGerd Hoffmann
qboot isn't a bios and shouldnt be named that way. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200915120909.20838-2-kraxel@redhat.com
2020-09-16Merge remote-tracking branch ↵Peter Maydell
'remotes/berrange/tags/block-odirect-pull-request' into staging block: improve error reporting for unsupported O_DIRECT # gpg: Signature made Wed 16 Sep 2020 10:45:48 BST # gpg: using RSA key DAF3A6FDB26B62912D0E8E3FBE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" [full] # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" [full] # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * remotes/berrange/tags/block-odirect-pull-request: block/file: switch to use qemu_open/qemu_create for improved errors util: give a specific error message when O_DIRECT doesn't work util: introduce qemu_open and qemu_create with error reporting util: add Error object for qemu_open_internal error reporting util: refactor qemu_open_old to split off variadic args handling util: rename qemu_open() to qemu_open_old() util: split off a helper for dealing with O_CLOEXEC flag monitor: simplify functions for getting a dup'd fdset entry Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-16Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20200915' ↵Peter Maydell
into staging The intention of the following two patches is making users aware about the negative file I/O performance impact when using a very low value for 9P client parameter 'msize', which especially is the case if no 'msize' parameter was supplied by the user with a 9P Linux client at all. All it does is logging a performance warning on host side (once) in that case. By setting 'msize' on client side to any value larger than 8192 the performance warning will disappear. See https://wiki.qemu.org/Documentation/9psetup#msize for details. # gpg: Signature made Tue 15 Sep 2020 11:37:32 BST # gpg: using RSA key 96D8D110CF7AF8084F88590134C2B58765A47395 # gpg: issuer "qemu_oss@crudebyte.com" # gpg: Good signature from "Christian Schoenebeck <qemu_oss@crudebyte.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: ECAB 1A45 4014 1413 BA38 4926 30DB 47C3 A012 D5F4 # Subkey fingerprint: 96D8 D110 CF7A F808 4F88 5901 34C2 B587 65A4 7395 * remotes/cschoenebeck/tags/pull-9p-20200915: 9pfs: disable msize warning for synth driver 9pfs: log warning if msize <= 8192 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-16util: rename qemu_open() to qemu_open_old()Daniel P. Berrangé
We want to introduce a new version of qemu_open() that uses an Error object for reporting problems and make this it the preferred interface. Rename the existing method to release the namespace for the new impl. Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2020-09-15virtio-gpu: build modularGerd Hoffmann
Only build virtio-gpu-device modular (the code which actually depends on the external virglrenderer library). virtio-gpu-pci and virtio-vga are compiled into core qemu still. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20200914134224.29769-7-kraxel@redhat.com
2020-09-15virtio-gpu: make virtio_gpu_ops staticGerd Hoffmann
Reference it via ops pointer instead, simliar to the vga one. Removes hard symbol reference, needed to build virtio-gpu modular. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20200914134224.29769-6-kraxel@redhat.com
2020-09-15meson: remove duplicate qxl sourcesGerd Hoffmann
We should add sources to the softmmu_ss or module_ss but not both. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20200914134224.29769-4-kraxel@redhat.com
2020-09-15meson: fix qxl dependenciesGerd Hoffmann
Add pixman and spice deps to qxl module. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20200914134224.29769-2-kraxel@redhat.com
2020-09-159pfs: disable msize warning for synth driverChristian Schoenebeck
Previous patch introduced a performance warning being logged on host side if client connected with an 'msize' <= 8192. Disable this performance warning for the synth driver to prevent that warning from being printed whenever the 9pfs (qtest) test cases are running. Introduce a new export flag V9FS_NO_PERF_WARN for that purpose, which might also be used to disable such warnings from the CLI in future. We could have also prevented the warning by simply raising P9_MAX_SIZE in virtio-9p-test.c to any value larger than 8192, however in the context of test cases it makes sense running for edge cases, which includes the lowest 'msize' value supported by the server which is 4096, hence we want to preserve an msize of 4096 for the test client. Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <E1kEyDy-0006nN-5A@lizzy.crudebyte.com> Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
2020-09-159pfs: log warning if msize <= 8192Christian Schoenebeck
It is essential to choose a reasonable high value for 'msize' to avoid severely degraded file I/O performance. This parameter can only be chosen on client/guest side, and a Linux client defaults to an 'msize' of only 8192 if the user did not explicitly specify a value for 'msize', which results in very poor file I/O performance. Unfortunately many users are not aware that they should specify an appropriate value for 'msize' to avoid severe performance issues, so log a performance warning (with a QEMU wiki link explaining this issue in detail) on host side in that case to make it more clear. Currently a client cannot automatically pick a reasonable value for 'msize', because a good value for 'msize' depends on the file I/O potential of the underlying storage on host side, i.e. a feature invisible to the client, and even then a user would still need to trade off between performance profit and additional RAM costs, i.e. with growing 'msize' (RAM occupation), performance still increases, but performance delta will shrink continuously. Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <e6fc84845c95816ad5baecb0abd6bfefdcf7ec9f.1599144062.git.qemu_oss@crudebyte.com> Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
2020-09-14hw/arm/npcm7xx: add board setup stub for CPU and UART clocksHavard Skinnemoen
When booting directly into a kernel, bypassing the boot loader, the CPU and UART clocks are not set up correctly. This makes the system appear very slow, and causes the initrd boot test to fail when optimization is off. The UART clock must run at 24 MHz. The default 25 MHz reference clock cannot achieve this, so switch to PLL2/2 @ 480 MHz, which works perfectly with the default /20 divider. The CPU clock should run at 800 MHz, so switch it to PLL1/2. PLL1 runs at 800 MHz by default, so we need to double the feedback divider as well to make it run at 1600 MHz (so PLL1/2 runs at 800 MHz). We don't bother checking for PLL lock because we know our emulated PLLs lock instantly. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-13-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsjHavard Skinnemoen
This allows these NPCM7xx-based boards to boot from a flash image, e.g. one built with OpenBMC. For example like this: IMAGE=${OPENBMC}/build/tmp/deploy/images/gsj/image-bmc qemu-system-arm -machine quanta-gsj -nographic \ -drive file=${IMAGE},if=mtd,bus=0,unit=0,format=raw,snapshot=on Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200911052101.2602693-12-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/ssi: NPCM7xx Flash Interface Unit device modelHavard Skinnemoen
This implements a device model for the NPCM7xx SPI flash controller. Direct reads and writes, and user-mode transactions have been tested in various modes. Protection features are not implemented yet. All the FIU instances are available in the SoC's address space, regardless of whether or not they're connected to actual flash chips. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-11-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/mem: Stubbed out NPCM7xx Memory Controller modelHavard Skinnemoen
This just implements the bare minimum to cause the boot block to skip memory initialization. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-10-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/nvram: NPCM7xx OTP device modelHavard Skinnemoen
This supports reading and writing OTP fuses and keys. Only fuse reading has been tested. Protection is not implemented. Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-9-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/arm: Load -bios image as a boot ROM for npcm7xxHavard Skinnemoen
If a -bios option is specified on the command line, load the image into the internal ROM memory region, which contains the first instructions run by the CPU after reset. If -bios is not specified, the vbootrom included with qemu is loaded by default. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-8-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/arm: Add two NPCM7xx-based machinesHavard Skinnemoen
This adds two new machines, both supported by OpenBMC: - npcm750-evb: Nuvoton NPCM750 Evaluation Board. - quanta-gsj: A board with a NPCM730 chip. They rely on the NPCM7xx SoC device to do the heavy lifting. They are almost completely identical at the moment, apart from the SoC type, which currently only changes the reset contents of one register (GCR.MDLR), but they might grow apart a bit more as more functionality is added. Both machines can boot the Linux kernel into /bin/sh. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-6-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/arm: Add NPCM730 and NPCM750 SoC modelsHavard Skinnemoen
The Nuvoton NPCM7xx SoC family are used to implement Baseboard Management Controllers in servers. While the family includes four SoCs, this patch implements limited support for two of them: NPCM730 (targeted for Data Center applications) and NPCM750 (targeted for Enterprise applications). This patch includes little more than the bare minimum needed to boot a Linux kernel built with NPCM7xx support in direct-kernel mode: - Two Cortex-A9 CPU cores with built-in periperhals. - Global Configuration Registers. - Clock Management. - 3 Timer Modules with 5 timers each. - 4 serial ports. The chips themselves have a lot more features, some of which will be added to the model at a later stage. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-5-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/timer: Add NPCM7xx Timer device modelHavard Skinnemoen
The NPCM730 and NPCM750 SoCs have three timer modules each holding five timers and some shared registers (e.g. interrupt status). Each timer runs at 25 MHz divided by a prescaler, and counts down from a configurable initial value to zero. When zero is reached, the interrupt flag for the timer is set, and the timer is disabled (one-shot mode) or reloaded from its initial value (periodic mode). This implementation is sufficient to boot a Linux kernel configured for NPCM750. Note that the kernel does not seem to actually turn on the interrupts. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-4-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/misc: Add NPCM7xx Clock Controller device modelHavard Skinnemoen
Enough functionality to boot the Linux kernel has been implemented. This includes: - Correct power-on reset values so the various clock rates can be accurately calculated. - Clock enables stick around when written. In addition, a best effort attempt to implement SECCNT and CNTR25M was made even though I don't think the kernel needs them. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-3-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/misc: Add NPCM7xx System Global Control Registers device modelHavard Skinnemoen
Implement a device model for the System Global Control Registers in the NPCM730 and NPCM750 BMC SoCs. This is primarily used to enable SMP boot (the boot ROM spins reading the SCRPAD register) and DDR memory initialization; other registers are best effort for now. The reset values of the MDLR and PWRON registers are determined by the SoC variant (730 vs 750) and board straps respectively. Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-2-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/arm: versal-virt: Correct the tx/rx GEM clocksEdgar E. Iglesias
Correct the GEMs tx/rx clocks to use the 125Mhz fixed-clock. This matches the setup with the fixed-link 100Mbit PHY. It also avoids the following warnings from the Linux kernel driver: eth0: unable to generate target frequency: 125000000 Hz Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20200909174647.662864-2-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/arm/mps2: New board model mps2-an500Peter Maydell
Implement a model of the MPS2 with the AN500 firmware. This is similar to the AN385, with the following differences: * Cortex-M7 CPU * PSRAM is at 0x6000_0000 * Ethernet is at 0xa000_0000 * No zbt_boot_ctrl remapping of the low 16K (but QEMU doesn't implement this anyway) * no "block RAM" at 0x01000000 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200903202048.15370-3-peter.maydell@linaro.org
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-06 13:00:49 +0000