aboutsummaryrefslogtreecommitdiff
path: root/hw
AgeCommit message (Expand)Author
2019-09-20Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-pull-reques...Peter Maydell
2019-09-19Merge remote-tracking branch 'remotes/kraxel/tags/ati-20190919-pull-request' ...Peter Maydell
2019-09-19Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' int...Peter Maydell
2019-09-19Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-sf1-v3...Peter Maydell
2019-09-19vfio: fix a typoChen Zhang
2019-09-19ati: use vga_read_byte in ati_cursor_defineGerd Hoffmann
2019-09-19vga: move access helpers to separate include fileGerd Hoffmann
2019-09-18trace: Remove trailing newline in eventsPhilippe Mathieu-Daudé
2019-09-18loader: Trace loaded imagesAlexey Kardashevskiy
2019-09-17riscv: sifive_u: Update model and compatible strings in device treeBin Meng
2019-09-17riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernetBin Meng
2019-09-17riscv: sifive_u: Fix broken GEM supportBin Meng
2019-09-17riscv: sifive_u: Instantiate OTP memory with a serial numberBin Meng
2019-09-17riscv: sifive: Implement a model for SiFive FU540 OTPBin Meng
2019-09-17riscv: sifive_u: Change UART node name in device treeBin Meng
2019-09-17riscv: sifive_u: Update UART base addresses and IRQsBin Meng
2019-09-17riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodesBin Meng
2019-09-17riscv: sifive_u: Add PRCI block to the SoCBin Meng
2019-09-17riscv: sifive_u: Generate hfclk and rtcclk nodesBin Meng
2019-09-17riscv: sifive: Implement PRCI model for FU540Bin Meng
2019-09-17riscv: sifive_u: Update PLIC hart topology configuration stringBin Meng
2019-09-17riscv: sifive_u: Update hart configuration to reflect the real FU540 SoCBin Meng
2019-09-17riscv: sifive_u: Set the minimum number of cpus to 2Bin Meng
2019-09-17riscv: hart: Add a "hartid-base" property to RISC-V hart arrayBin Meng
2019-09-17riscv: hart: Extract hart realize to a separate routineBin Meng
2019-09-17riscv: sifive_e: Drop sifive_mmio_emulate()Bin Meng
2019-09-17riscv: sifive_e: prci: Update the PRCI register block sizeBin Meng
2019-09-17riscv: sifive_e: prci: Fix a typo of hfxosccfg register programmingBin Meng
2019-09-17riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}Bin Meng
2019-09-17riscv: sifive_u: Remove the unnecessary include of prci headerBin Meng
2019-09-17riscv: hw: Remove the unnecessary include of target/riscv/cpu.hBin Meng
2019-09-17riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) insteadBin Meng
2019-09-17riscv: hw: Change create_fdt() to return voidBin Meng
2019-09-17riscv: hw: Remove not needed PLIC properties in device treeBin Meng
2019-09-17riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cellBin Meng
2019-09-17riscv: hw: Remove superfluous "linux, phandle" propertyBin Meng
2019-09-17riscv: hw: Remove duplicated "hw/hw.h" inclusionBin Meng
2019-09-17riscv: sifive_test: Add reset functionalityBin Meng
2019-09-17riscv: Resolve full path of the given bios imageBin Meng
2019-09-17riscv: Add a helper routine for finding firmwareBin Meng
2019-09-17riscv: plic: Remove unused interrupt functionsAlistair Francis
2019-09-17riscv: sifive_u: Fix clock-names property for ethernet nodeGuenter Roeck
2019-09-17riscv: sivive_u: Add dummy serial clock and aliases entry for uartGuenter Roeck
2019-09-17riscv: sifive_u: Add support for loading initrdGuenter Roeck
2019-09-17Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
2019-09-17Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
2019-09-16virtio-mmio: implement modern (v2) personality (virtio-1)Sergio Lopez
2019-09-16hw/i386/pc: Extract the x86 generic fw_cfg codePhilippe Mathieu-Daudé
2019-09-16hw/i386/pc: Rename pc_build_feature_control() as generic fw_cfg_build_*Philippe Mathieu-Daudé
2019-09-16hw/i386/pc: Let pc_build_feature_control() take a MachineState argumentPhilippe Mathieu-Daudé