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2018-08-20sun4u: ensure kernel_top is always initialisedMark Cave-Ayland
Valgrind reports that when loading a non-ELF kernel, kernel_top may be used uninitialised when checking for an initrd. Since there are no known non-ELF kernels for SPARC64 then we can simply initialise kernel_top to 0 and then skip the initrd load process if it hasn't been set by load_elf(). Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2018-08-20Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20180820' into stagingPeter Maydell
First round of s390x patches for 3.1: - add compat machine for 3.1 - remove deprecated 's390-squash-mcss' option - cpu models: add "max" cpu model, enhance feature group code - kvm: add support for etoken facility and huge page backing # gpg: Signature made Mon 20 Aug 2018 13:47:38 BST # gpg: using RSA key DECF6B93C6F02FAF # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" # gpg: aka "Cornelia Huck <cohuck@kernel.org>" # gpg: aka "Cornelia Huck <cohuck@redhat.com>" # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20180820: s390x: Enable KVM huge page backing support s390x/kvm: add etoken facility linux-headers: update s390x/cpumodel: Add "-cpu max" support s390x: remove 's390-squash-mcss' option s390x/cpumodel: enum type S390FeatGroup now gets generated s390x: introduce 3.1 compat machine Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-20Merge remote-tracking branch 'remotes/marcel/tags/rdma-pull-request' into ↵Peter Maydell
staging RDMA queue # gpg: Signature made Sat 18 Aug 2018 16:01:46 BST # gpg: using RSA key 36D4C0F0CF2FE46D # gpg: Good signature from "Marcel Apfelbaum <marcel.apfelbaum@zoho.com>" # gpg: aka "Marcel Apfelbaum <marcel@redhat.com>" # gpg: aka "Marcel Apfelbaum <marcel.apfelbaum@gmail.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: B1C6 3A57 F92E 08F2 640F 31F5 36D4 C0F0 CF2F E46D * remotes/marcel/tags/rdma-pull-request: config: split PVRDMA from RDMA hw/pvrdma: remove not needed include hw/rdma: Add reference to pci_dev in backend_dev hw/rdma: Bugfix - Support non-aligned buffers hw/rdma: Print backend QP number in hex format hw/rdma: Cosmetic change - move to generic function hw/pvrdma: Cosmetic change - indent right hw/rdma: Reorder resource cleanup hw/rdma: Do not allocate memory for non-dma MR hw/rdma: Delete useless structure RdmaRmUserMR hw/pvrdma: Make default pkey 0xFFFF hw/pvrdma: Clean CQE before use hw/rdma: Modify debug macros hw/pvrdma: Bugfix - provide the correct attr_mask to query_qp hw/rdma: Make distinction between device init and start modes Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-20s390x: remove 's390-squash-mcss' optionCornelia Huck
This option has been deprecated for two releases; remove it. Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Halil Pasic <pasic@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-20s390x: introduce 3.1 compat machineCornelia Huck
Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-20hw/dma/pl080: Remove hw_error() if DMA is enabledPeter Maydell
The PL08x model currently will unconditionally call hw_error() if the DMA engine is enabled by the guest. This has been present since the PL080 model was edded in 2006, and is presumably either unintentional debug code left enabled, or a guard against untested DMA engine code being used. Remove the hw_error(), since we now have a guest which will actually try to use the DMA engine (the self-test binary for the AN505 MPS2 FPGA image). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-08-20hw/dma/pl080: Correct bug in register address decode logicPeter Maydell
A bug in the handling of the register address decode logic for the PL08x meant that we were incorrectly treating accesses to the DMA channel registers (DMACCxSrcAddr, DMACCxDestaddr, DMACCxLLI, DMACCxControl, DMACCxConfiguration) as bad offsets. Fix this long-standing bug. Fixes: https://bugs.launchpad.net/qemu/+bug/1637974 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-08-20hw/dma/pl080: Provide device reset functionPeter Maydell
The PL080/PL081 model is missing a reset function; implement it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-08-20hw/dma/pl080: Don't use CPU address space for DMA accessesPeter Maydell
Currently our PL080/PL081 model uses a combination of the CPU's address space (via cpu_physical_memory_{read,write}()) and the system address space for performing DMA accesses. For the PL081s in the MPS FPGA images, their DMA accesses must go via Master Security Controllers. Switch the PL080/PL081 model to take a MemoryRegion property which defines its downstream for making DMA accesses. Since the PL08x are only used in two board models, we make provision of the 'downstream' link mandatory and convert both users at once, rather than having it be optional with a default to the system address space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-08-20hw/dma/pl080: Support all three interrupt linesPeter Maydell
The PL080 and PL081 have three outgoing interrupt lines: * DMACINTERR signals DMA errors * DMACINTTC is the DMA count interrupt * DMACINTR is a combined interrupt, the logical OR of the other two We currently only implement DMACINTR, because that's all the realview and versatile boards needed, but the instances of the PL081 in the MPS2 firmware images use all three interrupt lines. Implement the missing DMACINTERR and DMACINTTC. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-08-20hw/dma/pl080: Allow use as embedded-struct devicePeter Maydell
Create a new include file for the pl081's device struct, type macros, etc, so that it can be instantiated using the "embedded struct" coding style. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-08-20nvic: Expose NMI linePeter Maydell
On real v7M hardware, the NMI line is an externally visible signal that an SoC or board can toggle to assert an NMI. Expose it in our QEMU NVIC and armv7m container objects so that a board model can wire it up if it needs to. In particular, the MPS2 watchdog is wired to NMI. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-08-20hw/watchdog/cmsdk_apb_watchdog: Implement CMSDK APB watchdog modulePeter Maydell
The Arm Cortex-M System Design Kit includes a simple watchdog module based on a 32-bit down-counter. Implement this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-20hw/timer/m48t59: Move away from old_mmio accessorsPeter Maydell
Move the m48t59 device away from using old_mmio MemoryRegionOps accessors. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-id: 20180802180602.22047-1-peter.maydell@linaro.org
2018-08-20hw/misc: Remove mmio_interface devicePeter Maydell
The mmio_interface device was a purely internal artifact of the implementation of the memory subsystem's request_ptr APIs. Now that we have removed those APIs, we can remove the mmio_interface device too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com> Message-id: 20180817114619.22354-4-peter.maydell@linaro.org
2018-08-20hw/ssi/xilinx_spips: Remove unneeded MMIO request_ptr codePeter Maydell
We now support direct execution from MMIO regions in the core memory subsystem. This means that we don't need to have device-specific support for it, and we can remove the request_ptr handling from the Xilinx SPIPS device. (It was broken anyway due to race conditions, and disabled by default.) This device is the only in-tree user of this API. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com> Message-id: 20180817114619.22354-2-peter.maydell@linaro.org
2018-08-20sdhci: add i.MX SD Stable Clock bitHans-Erik Floryd
Add the ESDHC PRSSTAT_SDSTB bit, using the value of SDHC_CLOCK_INT_STABLE. Freescale recommends checking this bit when changing clock frequency. Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> Message-id: 1534507843-4251-1-git-send-email-hans-erik.floryd@rt-labs.com [PMM: fixed indentation] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-20hw/arm/virt: Add virt-3.1 machine typeAndrew Jones
Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-20imx_serial: Generate interrupt on receive data ready if enabledHans-Erik Floryd
Generate an interrupt if USR2_RDR and UCR4_DREN are both set. Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> Message-id: 1534341354-11956-1-git-send-email-hans-erik.floryd@rt-labs.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-20hw/intc/arm_gicv3_its: downgrade error_report to warn_report in ↵Jia He
kvm_arm_its_reset In scripts/arch-run.bash of kvm-unit-tests, it will check the qemu output log with: if [ -z "$(echo "$errors" | grep -vi warning)" ]; then Thus without the warning prefix, all of the test fail. Since it is not unrecoverable error in kvm_arm_its_reset for current implementation, downgrading the report from error to warn makes sense. Signed-off-by: Jia He <jia.he@hxt-semitech.com> Message-id: 1531969910-32843-1-git-send-email-jia.he@hxt-semitech.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-20Merge remote-tracking branch ↵Peter Maydell
'remotes/ehabkost/tags/machine-next-pull-request' into staging Machine queue, 2018-08-17 * Allow machine classes to specify if boot device suffixes should be ignored by get_boot_devices_list() * Tiny coding style fixup # gpg: Signature made Fri 17 Aug 2018 19:29:22 BST # gpg: using RSA key 2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/machine-next-pull-request: fw_cfg: ignore suffixes in the bootdevice list dependent on machine class sysbus: always allow explicit_ofw_unit_address() to override address generation machine: Fix coding style at machine_run_board_init() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-18config: split PVRDMA from RDMAMarcel Apfelbaum
In some BSD systems RDMA migration is possible while the pvrdma device can't be used because the mremap system call is missing. Reported-by: Rebecca Cran <rebecca@bluestop.org> Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <20180816151637.24553-1-marcel.apfelbaum@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com>
2018-08-18hw/pvrdma: remove not needed includeMarcel Apfelbaum
No need to include linux/types.h, is empty anyway. Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <20180811171534.11917-1-marcel.apfelbaum@gmail.com> Reviewed-by: Yuval Shaia <yuval.shaia@oracle.com>
2018-08-18hw/rdma: Add reference to pci_dev in backend_devYuval Shaia
The field backend_dev->dev is not initialized, fix it. Signed-off-by: Yuval Shaia <yuval.shaia@oracle.com> Message-Id: <20180805153518.2983-14-yuval.shaia@oracle.com> Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
2018-08-18hw/rdma: Bugfix - Support non-aligned buffersYuval Shaia
RDMA application can provide non-aligned buffers to be registered. In such case the DMA address passed by driver is pointing to the beginning of the physical address of the mapped page so we can't distinguish between two addresses from the same page. Fix it by keeping the offset of the virtual address in mr->virt. Signed-off-by: Yuval Shaia <yuval.shaia@oracle.com> Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <20180805153518.2983-13-yuval.shaia@oracle.com> Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
2018-08-18hw/rdma: Print backend QP number in hex formatYuval Shaia
To be consistent with other prints throughout the code fix places that print it as decimal number. Signed-off-by: Yuval Shaia <yuval.shaia@oracle.com> Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <20180805153518.2983-12-yuval.shaia@oracle.com> Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
2018-08-18hw/rdma: Cosmetic change - move to generic functionYuval Shaia
To ease maintenance of struct comp_thread move all related code to dedicated function. Signed-off-by: Yuval Shaia <yuval.shaia@oracle.com> Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <20180805153518.2983-11-yuval.shaia@oracle.com> Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
2018-08-18hw/pvrdma: Cosmetic change - indent rightYuval Shaia
Signed-off-by: Yuval Shaia <yuval.shaia@oracle.com> Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <20180805153518.2983-10-yuval.shaia@oracle.com> Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
2018-08-18hw/rdma: Reorder resource cleanupYuval Shaia
To be consistence with allocation do the reverse order in deallocation Signed-off-by: Yuval Shaia <yuval.shaia@oracle.com> Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <20180805153518.2983-9-yuval.shaia@oracle.com> Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
2018-08-18hw/rdma: Do not allocate memory for non-dma MRYuval Shaia
There is no use in the memory allocated for non-dma MR. Delete the code that allocates it. Signed-off-by: Yuval Shaia <yuval.shaia@oracle.com> Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <20180805153518.2983-8-yuval.shaia@oracle.com> Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
2018-08-18hw/rdma: Delete useless structure RdmaRmUserMRYuval Shaia
The structure RdmaRmUserMR has no benefits, remove it an move all its fields to struct RdmaRmMR. Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Signed-off-by: Yuval Shaia <yuval.shaia@oracle.com> Message-Id: <20180805153518.2983-7-yuval.shaia@oracle.com> Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
2018-08-18hw/pvrdma: Make default pkey 0xFFFFYuval Shaia
0x7FFF is not the default pkey - fix it. Signed-off-by: Yuval Shaia <yuval.shaia@oracle.com> Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <20180805153518.2983-6-yuval.shaia@oracle.com> Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
2018-08-18hw/pvrdma: Clean CQE before useYuval Shaia
Next CQE is fetched from CQ ring, clean it before usage as it still carries old CQE values. Signed-off-by: Yuval Shaia <yuval.shaia@oracle.com> Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <20180805153518.2983-5-yuval.shaia@oracle.com> Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
2018-08-18hw/rdma: Modify debug macrosYuval Shaia
- Add line counter to ease navigation in log - Print rdma instead of pvrdma Signed-off-by: Yuval Shaia <yuval.shaia@oracle.com> Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <20180805153518.2983-4-yuval.shaia@oracle.com> Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
2018-08-18hw/pvrdma: Bugfix - provide the correct attr_mask to query_qpYuval Shaia
Calling rdma_rm_query_qp with attr_mask equals to -1 leads to error where backend query_qp fails to retrieve the needed QP attributes. Fix it by providing the attr_mask we got from driver. Signed-off-by: Yuval Shaia <yuval.shaia@oracle.com> Message-Id: <20180805153518.2983-3-yuval.shaia@oracle.com> Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
2018-08-18hw/rdma: Make distinction between device init and start modesYuval Shaia
There are certain operations that are well considered as part of device configuration while others are needed only when "start" command is triggered by the guest driver. An example of device initialization step is msix_init and example of "device start" stage is the creation of a CQ completion handler thread. Driver expects such distinction - implement it. Signed-off-by: Yuval Shaia <yuval.shaia@oracle.com> Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <20180805153518.2983-2-yuval.shaia@oracle.com> Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
2018-08-17vfio/ccw/pci: Allow devices to opt-in for ballooningAlex Williamson
If a vfio assigned device makes use of a physical IOMMU, then memory ballooning is necessarily inhibited due to the page pinning, lack of page level granularity at the IOMMU, and sufficient notifiers to both remove the page on balloon inflation and add it back on deflation. However, not all devices are backed by a physical IOMMU. In the case of mediated devices, if a vendor driver is well synchronized with the guest driver, such that only pages actively used by the guest driver are pinned by the host mdev vendor driver, then there should be no overlap between pages available for the balloon driver and pages actively in use by the device. Under these conditions, ballooning should be safe. vfio-ccw devices are always mediated devices and always operate under the constraints above. Therefore we can consider all vfio-ccw devices as balloon compatible. The situation is far from straightforward with vfio-pci. These devices can be physical devices with physical IOMMU backing or mediated devices where it is unknown whether a physical IOMMU is in use or whether the vendor driver is well synchronized to the working set of the guest driver. The safest approach is therefore to assume all vfio-pci devices are incompatible with ballooning, but allow user opt-in should they have further insight into mediated devices. Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2018-08-17vfio: Inhibit ballooning based on group attachment to a containerAlex Williamson
We use a VFIOContainer to associate an AddressSpace to one or more VFIOGroups. The VFIOContainer represents the DMA context for that AdressSpace for those VFIOGroups and is synchronized to changes in that AddressSpace via a MemoryListener. For IOMMU backed devices, maintaining the DMA context for a VFIOGroup generally involves pinning a host virtual address in order to create a stable host physical address and then mapping a translation from the associated guest physical address to that host physical address into the IOMMU. While the above maintains the VFIOContainer synchronized to the QEMU memory API of the VM, memory ballooning occurs outside of that API. Inflating the memory balloon (ie. cooperatively capturing pages from the guest for use by the host) simply uses MADV_DONTNEED to "zap" pages from QEMU's host virtual address space. The page pinning and IOMMU mapping above remains in place, negating the host's ability to reuse the page, but the host virtual to host physical mapping of the page is invalidated outside of QEMU's memory API. When the balloon is later deflated, attempting to cooperatively return pages to the guest, the page is simply freed by the guest balloon driver, allowing it to be used in the guest and incurring a page fault when that occurs. The page fault maps a new host physical page backing the existing host virtual address, meanwhile the VFIOContainer still maintains the translation to the original host physical address. At this point the guest vCPU and any assigned devices will map different host physical addresses to the same guest physical address. Badness. The IOMMU typically does not have page level granularity with which it can track this mapping without also incurring inefficiencies in using page size mappings throughout. MMU notifiers in the host kernel also provide indicators for invalidating the mapping on balloon inflation, not for updating the mapping when the balloon is deflated. For these reasons we assume a default behavior that the mapping of each VFIOGroup into the VFIOContainer is incompatible with memory ballooning and increment the balloon inhibitor to match the attached VFIOGroups. Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2018-08-17kvm: Use inhibit to prevent ballooning without synchronous mmuAlex Williamson
Remove KVM specific tests in balloon_page(), instead marking ballooning as inhibited without KVM_CAP_SYNC_MMU support. Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2018-08-16fw_cfg: ignore suffixes in the bootdevice list dependent on machine classMark Cave-Ayland
For the older machines (such as Mac and SPARC) the DT nodes representing bootdevices for disk nodes are irregular for mainly historical reasons. Since the majority of bootdevice nodes for these machines either do not have a separate disk node or require different (custom) names then it is much easier for processing to just disable all suffixes for a particular machine. Introduce a new ignore_boot_device_suffixes MachineClass property to control bootdevice suffix generation, defaulting to false in order to preserve compatibility. Suggested-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20180810124027.10698-1-mark.cave-ayland@ilande.co.uk> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16sysbus: always allow explicit_ofw_unit_address() to override address generationMark Cave-Ayland
Some SysBusDevices either use sysbus_init_mmio() without sysbus_mmio_map() or the first MMIO memory region doesn't represent the bus address, causing a firmware device path with an invalid address to be generated. SysBusDeviceClass does provide a virtual explicit_ofw_unit_address() method that can be used to override this process, but it was originally intended only as as a fallback option meaning that any existing MMIO memory regions still take priority whilst determining the firmware device address. There is currently only one user of explicit_ofw_unit_address() and that is the PCI expander bridge (PXB) device which has no MMIO/PIO resources defined. This enables us to allow explicit_ofw_unit_address() to take priority without affecting backwards compatibility, allowing the address to be customised as required. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20180805112850.26063-2-mark.cave-ayland@ilande.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16machine: Fix coding style at machine_run_board_init()Dou Liyang
Commit 7747abf11487 ("hw/machine: Remove the Zero check of nb_numa_nodes for numa_complete_configuration()") removed the curly brackets. Re-add them. Signed-off-by: Dou Liyang <douly.fnst@cn.fujitsu.com> Message-Id: <20180710105129.23296-1-douly.fnst@cn.fujitsu.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> [ehabkost: rewrote commit message] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj()Thomas Huth
Now that we've got the common sysbus_init_child_obj() function, we do not need the local init_sysbus_child() anymore. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 1534420566-15799-1-git-send-email-thuth@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16aspeed: add a max_ram_size property to the memory controllerCédric Le Goater
This will be used to construct a memory region beyond the RAM region to let firmwares scan the address space with load/store to guess how much RAM the SoC has. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180807075757.7242-7-joel@jms.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16aspeed_sdmc: Handle ECC trainingJoel Stanley
This is required to ensure u-boot SDRAM training completes. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180807075757.7242-6-joel@jms.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16aspeed_sdmc: Init status always idleJoel Stanley
The ast2500 SDRAM training routine busy waits on the 'init cycle busy state' bit in DDR PHY Control/Status register #1 (MCR60). This ensures the bit always reads zero, and allows training to complete with upstream u-boot on the ast2500-evb. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180807075757.7242-5-joel@jms.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16aspeed_sdmc: Set 'cache initial sequence' always trueJoel Stanley
The SDRAM training routine sets the 'Enable cache initial' bit, and then waits for the 'cache initial sequence' to be done. Have it always return done, as there is no other side effects that the model needs to implement. This allows the upstream u-boot training to proceed on the ast2500-evb board. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180807075757.7242-4-joel@jms.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16aspeed_sdmc: Fix saved valuesJoel Stanley
This fixes the intended protection of read-only values in the configuration register. They were being always set to zero by mistake. The read-only fields depend on the configured memory size of the system, so they cannot be fixed at compile time. The most straight forward option was to store them in the state structure. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180807075757.7242-3-joel@jms.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16imx_spi: Unset XCH when TX FIFO becomes emptyTrent Piepho
The current emulation will clear the XCH bit when a burst finishes. This is not quite correct. According to the i.MX7d referemce manual, Rev 0.1, §10.1.7.3: This bit [XCH] is cleared automatically when all data in the TXFIFO and the shift register has been shifted out. So XCH should be cleared when the FIFO empties, not on completion of a burst. The FIFO is 64 x 32 bits = 2048 bits, while the max burst size is larger at 4096 bits. So it's possible that the burst is not finished after the TXFIFO empties. Sending a large block (> 2048 bits) with the Linux driver will use a burst that is larger than the TXFIFO. After the TXFIFO has emptied XCH does not become unset, as the burst is not yet finished. What should happen after the TXFIFO empties is the driver will refill it and set XCH. The rising edge of XCH will trigger another transfer to begin. However, since the emulation does not set XCH to 0, there is no rising edge and the next trasfer never begins. Signed-off-by: Trent Piepho <tpiepho@impinj.com> Message-id: 20180731201056.29257-1-tpiepho@impinj.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16loader: Implement .hex file loaderSu Hang
This patch adds Intel Hexadecimal Object File format support to the generic loader device. The file format specification is available here: http://www.piclist.com/techref/fileext/hex/intel.htm This file format is often used with microcontrollers such as the micro:bit, Arduino, STM32, etc. Users expect to be able to run .hex files directly with without first converting them to ELF. Most micro:bit code is developed in web-based IDEs without direct user access to binutils so it is important for QEMU to handle this file format natively. Signed-off-by: Su Hang <suhang16@mails.ucas.ac.cn> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20180814162739.11814-6-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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