Age | Commit message (Collapse) | Author | |
---|---|---|---|
2011-09-10 | target-xtensa: implement CPENABLE and PRID SRs | Max Filippov | |
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com> | |||
2011-09-10 | target-xtensa: add sample board | Max Filippov | |
Sample board and sample CPU core are used for debug and may be used for development of custom SoC emulators. This board has two fixed size memory regions for DTCM and ITCM and variable length SRAM region. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com> |