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path: root/hw/sun4m.c
AgeCommit message (Expand)Author
2007-12-29 M48T02 support (Robert Reif)blueswir1
2007-12-28 Initial support for SS-2 (Sun4c)blueswir1
2007-12-28 Initial support for Sun4d machines (SS-1000, SS-2000)blueswir1
2007-12-27 Add ID registerblueswir1
2007-12-17 Only create as many per CPU timers as there are CPUs. (Robert Reif)blueswir1
2007-12-10 Add SPARCstation 20 machine type (Robert Reif)blueswir1
2007-12-09 Add support for eccmemctl (Robert Reif)blueswir1
2007-12-04 No keyboard mode (Robert Reif)blueswir1
2007-12-02Add -drive parameter, by Laurent Vivier.ths
2007-11-28Use slavio base as boot prom address, rearrange sun4m init codeblueswir1
2007-11-18 Remove unused parameters from QEMUMachineInitFunc (Laurent Vivier)blueswir1
2007-11-17Break up vl.h.pbrook
2007-11-17 Machine specific IOMMU version (Robert Reif)blueswir1
2007-11-14Update OHW interface to version 3.blueswir1
2007-11-11 Add SPARCserver 600MP emulation (original patch by Robert Reif)blueswir1
2007-11-10added cpu_model parameter to cpu_init()bellard
2007-11-04 Remove target dependent codeblueswir1
2007-10-31Set boot sequence from command line (Dan Kenigsberg).balrog
2007-10-14 SuperSparc MXCC support (Robert Reif)blueswir1
2007-10-06 More detabificationblueswir1
2007-10-06 Implement user mode for timersblueswir1
2007-10-06 Support for loading a real BIOS image (Robert Reif)blueswir1
2007-10-05New '-bios' option, used to select an alternate BIOS image from bios_dir.j_mayer
2007-10-02 Fix kernel loadingblueswir1
2007-09-24 CPU boot modeblueswir1
2007-09-16find -type f | xargs sed -i 's/[\t ]$//g' # on most filesths
2007-08-16 Use qemu_irq for a reset signal between DMA and ESP/Lanceblueswir1
2007-08-04 Fix Sparc32 interrupt handlingblueswir1
2007-06-25 Rename variables and rearrange code to please gcc -Wshadow checksblueswir1
2007-05-27New option -net nic,model=? (Mark Glines)blueswir1
2007-05-27Handle unconnected vlan case in lanceblueswir1
2007-05-27Use qemu_irqs between CPUs and interrupt controllerblueswir1
2007-05-27Use qemu_irq between interrupt controller and timersblueswir1
2007-05-27Use qemu_irqs between dma controllers and esp, lanceblueswir1
2007-05-26Split DMA controller in twoblueswir1
2007-05-19Use full 36-bit physical address space on SS10blueswir1
2007-05-17Set limits for memory size to avoid overlap with devicesblueswir1
2007-05-17Force the primary CPU to run and other CPUs to halt, recalculate timersblueswir1
2007-05-06Fix slavio_misc baseblueswir1
2007-05-01Set OpenBIOS variables in NVRAMblueswir1
2007-04-21TCX 24 bit model supportblueswir1
2007-04-07Fix TCX base on SS10blueswir1
2007-04-07Unify IRQ handling.pbrook
2007-04-05Fill in real SparcStation 10 valuesblueswir1
2007-04-01Improved initrd support for mips.ths
2007-04-01Change Sparc uses of pic_set_irq to pic_set_irq_newblueswir1
2007-04-01Add SparcStation-10 machineblueswir1
2007-04-01Reorganise Sun4m to allow other machine typesblueswir1
2007-03-25Sparc32/64 CPU selectionblueswir1
2007-03-05New -cpu options: choose CPU model for emulated target.j_mayer
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