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2012-03-14sh4 hw/: Don't use CPUStateAndreas Färber
Scripted conversion: for file in hw/sh.h hw/shix.c hw/r2d.c; do sed -i "s/CPUState/CPUSH4State/g" $file done Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
2011-11-24sh_serial: convert to memory APIBenoît Canet
Signed-off-by: Benoit Canet <benoit.canet@gmail.com> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-24sh_timer: convert to memory APIBenoît Canet
Signed-off-by: Benoit Canet <benoit.canet@gmail.com> Signed-off-by: Avi Kivity <avi@redhat.com>
2011-11-24sh7750: convert memory controller/ioport to memory APIBenoît Canet
Signed-off-by: Benoit Canet <benoit.canet@gmail.com> Signed-off-by: Avi Kivity <avi@redhat.com>
2009-10-01Revert "Get rid of _t suffix"Anthony Liguori
In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01Get rid of _t suffixmalc
Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
2009-08-27ide: split away ide-mmio.cGerd Hoffmann
create ide-mmio.c and place mmio support there. only build ide-mmio support for platforms using it. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2008-12-07SH4: Eliminate P4 to A7 mangling (Takashi YOSHII).balrog
Main purpose of this is to delete *physical = address & 0x1fffffff; at target-sh4/helper.c:449, using new mmio rule introduced by #5849 This masking is a nice trick to realize P4/A7 duality of SH registers. But, IMHO, it is logically wrong. Most of SH4 cpu control registers in P4 area(0xfc000000...0xffffffff) have one more address called A7 which is usually P4 address with upper 3bits masked. This is an address only appears in TLB's physical address part. Current code use trick writing drivers as if they are really in A7 (that's why you see many *_A7 in hw/sh*.c), and using translation P4 to A7. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5935 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07sh4: Add IRL (4-bit encoded interrupt input) support (Takashi YOSHII).balrog
This patch adds IRL(4bit encoded 15 level interrupt input) support to SH using qemu_irq as a multi level (!=on/off) signal. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5925 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07sh4: mmio based CF support on r2d board (Takashi YOSHII).balrog
This patch adds emulation for a CompactFlash on sh4/r2d board. The device is CF, but wired to be worked as True-IDE mode, and connected directly to SH bus. So, this code is to support generally mmio based IDEs which are supported by "pata_platform" driver in linux kernel. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5924 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-21SH4: Switch serial emulation to qemu_irqaurel32
This patches makes SH serial emulation use qemu_irq in its interface. * hw/sh.h (sh_serial_init): Take qemu_irq, not intc_source. * hw/sh7750.c (sh7750_init): Adjust. * hw/sh_intc.c (sh_intc_set_irq): Don't assert or deassert irq more than once. * hw/sh_serial.c (sh_serial_state): Use qemu_irq, not intc_source. (sh_serial_clear_fifo, sh_serial_ioport_write) (sh_serial_receive_byte): Adjust. (sh_serial_init): Take qemu_irq, not intc_source. (Vladimir Prus) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5769 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-21SH4: Use qemu_irq in timer emulation.aurel32
* hw/sh.h (tmu012_init): Accept qemu_irq, not intc_source. * hw/sh7750.c (sh7750_init): Pass qemu_irq to tmu012_init. * hw/sh_intc.c (sh_intc_set_irq): New. (sh_intc_init): Allocate irqs. * hw/sh_intc.h (struct intc_desc): New field irqs. * hw/sh_timer.c (sh_timer_state): Use qemu_irq, not intc_source. (sh_timer_update): Use qemu_set_irq, not sh_intc_toggle_source. (sh_timer_init, tmu012_init): Adjust. (Vladimir Prus) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5768 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-14Fix warnings that would be caused by gcc flag -Wwrite-stringsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5206 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-09SH4 serial controler improvementsaurel32
(Shin-ichiro KAWASAKI) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4397 c046a42c-6fe2-441c-8c8c-71466251a162
2007-12-12Adds interrupt support to the sh specific timer code (Magnus Damm).balrog
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3812 c046a42c-6fe2-441c-8c8c-71466251a162
2007-11-17Break up vl.h.pbrook
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3674 c046a42c-6fe2-441c-8c8c-71466251a162