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AgeCommit message (Expand)Author
2023-01-06hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initializationBin Meng
2023-01-06hw/riscv: virt: Fix the value of "riscv, ndev" in the dtbBin Meng
2023-01-06hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"Bin Meng
2023-01-06hw/riscv: spike: Remove misleading commentsBin Meng
2023-01-06hw/riscv: Sort machines Kconfig options in alphabetical orderBin Meng
2023-01-06hw/riscv: Fix opentitan dependency to SIFIVE_PLICBin Meng
2023-01-06hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLICBin Meng
2023-01-06hw/{misc, riscv}: pfsoc: add system controller as unimplementedConor Dooley
2023-01-06hw/riscv: pfsoc: add missing FICs as unimplementedConor Dooley
2023-01-06hw/riscv: virt: Remove the redundant ipi-id propertyAtish Patra
2023-01-06hw/riscv/opentitan: add aon_timer base unimplWilfred Mallawa
2023-01-06hw/riscv/opentitan: bump opentitanWilfred Mallawa
2022-10-27riscv: re-randomize rng-seed on rebootJason A. Donenfeld
2022-10-17hw/riscv: set machine->fdt in spike_board_init()Daniel Henrique Barboza
2022-10-17hw/riscv: set machine->fdt in sifive_u_machine_init()Daniel Henrique Barboza
2022-10-14hw/riscv: virt: Enable booting S-mode firmware from pflashSunil V L
2022-10-14hw/riscv: virt: Move create_fw_cfg() prior to loading kernelSunil V L
2022-10-14hw/riscv: Update comment for qtest check in riscv_find_firmware()Bin Meng
2022-09-27hw/riscv: opentitan: Expose the resetvec as a SoC propertyAlistair Francis
2022-09-27hw/riscv: opentitan: Fixup resetvecAlistair Francis
2022-09-07hw/riscv: virt: Add PMU DT node to the device treeAtish Patra
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel
2022-09-07hw/riscv: virt: fix syscon subnode pathsConor Dooley
2022-09-07hw/riscv: virt: fix the plic's address cellsConor Dooley
2022-09-07hw/riscv: virt: fix uart node nameConor Dooley
2022-09-07hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripheralsConor Dooley
2022-09-07hw/riscv: opentitan: bump opentitan versionWilfred Mallawa
2022-09-07hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()Daniel Henrique Barboza
2022-09-07hw/riscv: virt: pass random seed to fdtJason A. Donenfeld
2022-07-03hw/riscv: boot: Reduce FDT address alignment constraintsAlistair Francis
2022-06-10hw/core/loader: return image sizes as ssize_tJamie Iles
2022-06-10hw/riscv: virt: Generate fw_cfg DT node correctlyAtish Patra
2022-05-24hw/riscv: virt: Fix interrupt parent for dynamic platform devicesAnup Patel
2022-05-24hw/riscv/sifive_u: Resolve redundant property accessorsBernhard Beschow
2022-05-24hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)Tsukasa OI
2022-05-24hw/riscv: Make CPU config error handling generous (virt/spike)Tsukasa OI
2022-04-29hw/riscv: Enable TPM backendsAlistair Francis
2022-04-29hw/riscv: virt: Add device plug supportAlistair Francis
2022-04-29hw/riscv: virt: Add support for generating platform FDT entriesAlistair Francis
2022-04-29hw/riscv: virt: Create a platform busAlistair Francis
2022-04-29hw/riscv: virt: Add a machine done notifierAlistair Francis
2022-04-29hw/riscv: Don't add empty bootargs to device treeBin Meng
2022-04-29hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionallyBin Meng
2022-04-22hw/riscv: boot: Support 64bit fdt address.Dylan Jhong
2022-04-22hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabledNiklas Cassel
2022-04-22hw/riscv: virt: Exit if the user provided -bios in combination with KVMRalf Ramsauer
2022-04-22riscv: opentitan: Connect opentitan SPI HostWilfred Mallawa
2022-04-06Remove qemu-common.h include from most unitsMarc-André Lureau
2022-03-03hw: riscv: opentitan: fixup SPI addressesWilfred Mallawa
2022-03-03hw/riscv: virt: Increase maximum number of allowed CPUsAnup Patel
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