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2024-08-19Revert "hw/riscv/virt.c: imsics DT: add '#msi-cells'"Andrew Jones
This reverts commit f42cdf2ea5b3a1dc369792d7acbf9cd3e5c90815. Linux does not properly handle '#msi-cells=<0>' when searching for MSI controllers for PCI devices which results in the devices being unable to use MSIs. A patch for Linux has been sent[1] but until it, or something like it, is merged and in distro kernels we should stop adding the property. It's harmless to stop adding it since the absence of the property and a value of zero for the property mean the same thing according to the DT binding definition. Link: https://lore.kernel.org/all/20240816124957.130017-2-ajones@ventanamicro.com/ # 1 Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240816160743.220374-5-ajones@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-07-22hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UARTSunil V L
The requirement ACPI_060 in the RISC-V BRS specification [1], requires NS16550 compatible UART to have the HID RSCV0003. So, update the HID for the UART. [1] - https://github.com/riscv-non-isa/riscv-brs/releases/download/v0.0.2/riscv-brs-spec.pdf (Chapter 6) Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240716144306.2432257-3-sunilvl@ventanamicro.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-07-22hw/riscv/virt-acpi-build.c: Add namespace devices for PLIC and APLICSunil V L
As per the requirement ACPI_080 in the RISC-V Boot and Runtime Services (BRS) specification [1], PLIC and APLIC should be in namespace as well. So, add them using the defined HID. [1] - https://github.com/riscv-non-isa/riscv-brs/releases/download/v0.0.2/riscv-brs-spec.pdf (Chapter 6) Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240716144306.2432257-2-sunilvl@ventanamicro.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-07-18hw/riscv/virt.c: re-insert and deprecate 'riscv,delegate'Daniel Henrique Barboza
Commit b1f1e9dcfa renamed 'riscv,delegate' to 'riscv,delegation' since it is the correct name as per dt-bindings, and the absence of the correct name will result in validation fails when dumping the dtb and using dt-validate. But this change has a side-effect: every other firmware available that is AIA capable is using 'riscv,delegate', and it will fault/misbehave if this property isn't present. The property was added back in QEMU 7.0, meaning we have 2 years of firmware development using the wrong property. Re-introducing 'riscv,delegate' while keeping 'riscv,delegation' allows older firmwares to keep booting with the 'virt' machine. 'riscv,delegate' is then marked for future deprecation with its use being discouraged from now on. Cc: Conor Dooley <conor@kernel.org> Cc: Anup Patel <apatel@ventanamicro.com> Fixes: b1f1e9dcfa ("hw/riscv/virt.c: aplic DT: rename prop to 'riscv, delegation'") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240715090455.145888-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26hw/riscv/virt.c: Make block devices default to virtioSunil V L
RISC-V virt is currently missing default type for block devices. Without this being set, proper backend is not created when option like -cdrom is used. So, make the virt board's default block device type be IF_VIRTIO similar to other architectures. We also need to set no_cdrom to avoid getting a default cdrom device. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240620064718.275427-1-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26hw/riscv/virt.c: imsics DT: add '#msi-cells'Daniel Henrique Barboza
The DT docs for riscv,imsics [1] requires a 'msi-cell' property. Add one and set it zero. [1] Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml Reported-by: Conor Dooley <conor@kernel.org> Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240531202759.911601-9-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26hw/riscv/virt.c: imsics DT: add 'qemu, imsics' to 'compatible'Daniel Henrique Barboza
The DT docs for riscv,imsics [1] predicts a 'qemu,imsics' enum in the 'compatible' property. [1] Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml Reported-by: Conor Dooley <conor@kernel.org> Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240531202759.911601-8-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26hw/riscv/virt.c: change imsic nodename to 'interrupt-controller'Daniel Henrique Barboza
The Linux DT docs for imsic [1] predicts an 'interrupt-controller@addr' node, not 'imsic@addr', given this node inherits the 'interrupt-controller' node. [1] Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml Reported-by: Conor Dooley <conor@kernel.org> Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240531202759.911601-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26hw/riscv/virt.c: aplic DT: rename prop to 'riscv, delegation'Daniel Henrique Barboza
The DT docs for riscv,aplic [1] predicts a 'riscv,delegation' property. Not 'riscv,delegate'. [1] Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml Reported-by: Conor Dooley <conor@kernel.org> Fixes: e6faee65855b ("hw/riscv: virt: Add optional AIA APLIC support to virt machine") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240531202759.911601-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26hw/riscv/virt.c: aplic DT: add 'qemu, aplic' to 'compatible'Daniel Henrique Barboza
The DT docs for riscv,aplic [1] predicts a 'qemu,aplic' enum in the 'compatible' property. [1] Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml Reported-by: Conor Dooley <conor@kernel.org> Fixes: e6faee65855b ("hw/riscv: virt: Add optional AIA APLIC support to virt machine") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240531202759.911601-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26hw/riscv/virt.c: rename aplic nodename to 'interrupt-controller'Daniel Henrique Barboza
The correct name of the aplic controller node, as per Linux kernel DT docs [1], is 'interrupt-controller@addr'. [1] Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml Reported-by: Conor Dooley <conor@kernel.org> Fixes: e6faee65855b ("hw/riscv: virt: Add optional AIA APLIC support to virt machine") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240531202759.911601-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26hw/riscv/virt.c: add aplic nodename helperDaniel Henrique Barboza
We'll change the aplic DT nodename in the next patch and the name is hardcoded in 2 different functions. Create a helper to change a single place later. While we're at it, in create_fdt_socket_aplic(), move 'aplic_name' inside the conditional to avoid allocating a string that won't be used when socket == NULL. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240531202759.911601-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26hw/riscv/virt.c: add address-cells in create_fdt_one_aplic()Daniel Henrique Barboza
We need #address-cells properties in all interrupt controllers that are referred by an interrupt-map [1]. For the RISC-V machine, both PLIC and APLIC controllers must have this property. PLIC already sets it in create_fdt_socket_plic(). Set the property for APLIC in create_fdt_one_aplic(). [1] https://lore.kernel.org/linux-arm-kernel/CAL_JsqJE15D-xXxmELsmuD+JQHZzxGzdXvikChn6KFWqk6NzPw@mail.gmail.com/ Suggested-by: Anup Patel <apatel@ventanamicro.com> Fixes: e6faee65855b ("hw/riscv: virt: Add optional AIA APLIC support to virt machine") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240531202759.911601-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-19hw/smbios: Remove 'uuid_encoded' argument from smbios_set_defaults()Philippe Mathieu-Daudé
'uuid_encoded' is always true, remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240617071118.60464-12-philmd@linaro.org>
2024-06-03hw/riscv/boot.c: Support 64-bit address for initrdCheng Yang
Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell() to set the address of initrd in FDT to support 64-bit address. Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-05-10kconfig: express dependency of individual boards on libfdtPaolo Bonzini
Now that boards are enabled by default and the "CONFIG_FOO=y" entries are gone from configs/devices/, there cannot be any more a conflicts between the default contents of configs/devices/ and a failed "depends on" clause. With this change, each individual board or target can express whether it needs FDT. It can then include the common code in the build via "select DEVICE_TREE", which will also as tell meson to link with libfdt. This allows building non-microvm x86 emulators without having libfdt available. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-05-10meson: pick libfdt from common_ss when building target-specific filesPaolo Bonzini
Avoid having to list dependencies such as libfdt twice, both on common_ss and specific_ss. Instead, just take all the dependencies in common_ss and allow the target-specific libqemu-*.fa library to use them. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-05-03riscv: switch boards to "default y"Paolo Bonzini
Some targets use "default y" for boards to filter out those that require TCG. For consistency we are switching all other targets to do the same. Continue with RISC-V. No changes to generated config-devices.mak file. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-04-25hw: Add a Kconfig switch for the TYPE_CPU_CLUSTER deviceThomas Huth
The cpu-cluster device is only needed for some few arm and riscv machines. Let's avoid compiling and linking it if it is not really necessary. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240415065655.130099-3-thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-04-25hw/riscv/virt: Replace sprintf by g_strdup_printfPhilippe Mathieu-Daudé
sprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1. Use g_strdup_printf instead. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> [rth: Use g_strdup_printf] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240412073346.458116-26-richard.henderson@linaro.org>
2024-03-22target/riscv/kvm: fix timebase-frequency when using KVM accelerationYong-Xuan Wang
The timebase-frequency of guest OS should be the same with host machine. The timebase-frequency value in DTS should be got from hypervisor when using KVM acceleration. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Message-ID: <20240314061510.9800-1-yongxuan.wang@sifive.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-03-18smbios: get rid of global smbios_ep_typeIgor Mammedov
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Ani Sinha <anisinha@redhat.com> Tested-by: Fiona Ebner <f.ebner@proxmox.com> Message-Id: <20240314152302.2324164-14-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-03-18smbios: get rid of smbios_legacy globalIgor Mammedov
clean up smbios_set_defaults() which is reused by legacy and non legacy machines from being aware of 'legacy' notion and need to turn it off. And push legacy handling up to PC machine code where it's relevant. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Ani Sinha <anisinha@redhat.com> Acked-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Tested-by: Fiona Ebner <f.ebner@proxmox.com> Message-Id: <20240314152302.2324164-7-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-03-08target/riscv: fix ACPI MCFG tableIlya Chugin
MCFG segments should point to PCI configuration range, not BAR MMIO. Signed-off-by: Ilya Chugin <danger_mail@list.ru> Fixes: 55ecd83b36 ("hw/riscv/virt-acpi-build.c: Add IO controllers and devices") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Message-ID: <180d236d-c8e4-411a-b4d2-632eb82092fa@list.ru> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-03-08hw/riscv/virt.c: make aclint compatible with 'qtest' accelDaniel Henrique Barboza
The 'virt' machine makes assumptions on the Advanced Core-Local Interruptor, or aclint, based on 'tcg_enabled()' conditionals. This will impact MSI related tests support when adding a RISC-V 'virt' libqos machine. The accelerator used in that case, 'qtest', isn't being accounted for and we'll error out if we try to enable aclint. Create a new virt_aclint_allowed() helper to gate the aclint code considering both TCG and 'qtest' accelerators. The error message is left untouched, mentioning TCG only, because we don't expect the regular user to be aware of 'qtest'. We want to add 'qtest' support for aclint only, leaving the TCG specific bits out of it. This is done by changing the current format we use today: if (tcg_enabled()) { if (s->have_aclint) { - aclint logic - } else { - non-aclint, TCG logic - } } into: if (virt_aclint_allowed() && s->have_aclint) { - aclint logic - } else if (tcg_enabled()) { - non-aclint, TCG logic - } Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240217192607.32565-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-03-08hw/riscv/virt.c: add virtio-iommu-pci hotplug supportDaniel Henrique Barboza
We want to add a RISC-V 'virt' libqos machine to increase our test coverage. Some of the tests will try to plug a virtio-iommu-pci device into the board and do some tests with it. Enable virtio-iommu-pci in the 'virt' machine. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240217192607.32565-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-03-08hw/riscv/virt.c: create '/soc/pci@...' fdt node earlierDaniel Henrique Barboza
Hotplugged FDT nodes will attempt to write this node that, at this moment, is being created only in create_fdt_pcie() during finalize_fdt(). Create it earlier. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240217192607.32565-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-03-08hw/riscv/virt-acpi-build.c: Add SRAT and SLIT ACPI tablesHaibo Xu
Enable ACPI NUMA support by adding the following 2 ACPI tables: SRAT: provides the association for memory/Harts and Proximity Domains SLIT: provides the relative distance between Proximity Domains The SRAT RINTC Affinity Structure definition[1] was based on the recently approved ACPI CodeFirst ECR[2]. [1] https://github.com/riscv-non-isa/riscv-acpi/issues/25 [2] https://mantis.uefi.org/mantis/view.php?id=2433 Signed-off-by: Haibo Xu <haibo1.xu@intel.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20240129094200.3581037-1-haibo1.xu@intel.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-03-08hw: riscv: Allow large kernels to boot by moving the initrd further away in RAMAlexandre Ghiti
Currently, the initrd is placed at 128MB, which overlaps with the kernel when it is large (for example syzbot kernels are). From the kernel side, there is no reason we could not push the initrd further away in memory to accommodate large kernels, so move the initrd at 512MB when possible. The ideal solution would have been to place the initrd based on the kernel size but we actually can't since the bss size is not known when the image is loaded by load_image_targphys_as() and the initrd would then overlap with this section. Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240206154042.514698-1-alexghiti@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-03-08hw/riscv/virt-acpi-build.c: Generate SPCR tableSia Jee Heng
Generate Serial Port Console Redirection Table (SPCR) for RISC-V virtual machine. Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240129021440.17640-3-jeeheng.sia@starfivetech.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-02-09target/riscv: SMBIOS support for RISC-V virt machineHeinrich Schuchardt
Generate SMBIOS tables for the RISC-V mach-virt. Add CONFIG_SMBIOS=y to the RISC-V default config. Set the default processor family in the type 4 table. The implementation is based on the corresponding ARM and Loongson code. With the patch the following firmware tables are provided: etc/smbios/smbios-anchor etc/smbios/smbios-tables Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20240123184229.10415-4-heinrich.schuchardt@canonical.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-02-09target/riscv: support new isa extension detection devicetree propertiesConor Dooley
A few months ago I submitted a patch to various lists, deprecating "riscv,isa" with a lengthy commit message [0] that is now commit aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") in the Linux kernel tree. Primarily, the goal was to replace "riscv,isa" with a new set of properties that allowed for strictly defining the meaning of various extensions, where "riscv,isa" was tied to whatever definitions inflicted upon us by the ISA manual, which have seen some variance over time. Two new properties were introduced: "riscv,isa-base" and "riscv,isa-extensions". The former is a simple string to communicate the base ISA implemented by a hart and the latter an array of strings used to communicate the set of ISA extensions supported, per the definitions of each substring in extensions.yaml [1]. A beneficial side effect was also the ability to define vendor extensions in a more "official" way, as the ISA manual and other RVI specifications only covered the format for vendor extensions in the ISA string, but not the meaning of vendor extensions, for obvious reasons. Add support for setting these two new properties in the devicetrees for the various devicetree platforms supported by QEMU for RISC-V. The Linux kernel already supports parsing ISA extensions from these new properties, and documenting them in the dt-binding is a requirement for new extension detection being added to the kernel. A side effect of the implementation is that the meaning for elements in "riscv,isa" and in "riscv,isa-extensions" are now tied together as they are constructed from the same source. The same applies to the ISA string provided in ACPI tables, but there does not appear to be any strict definitions of meanings in ACPI land either. Link: https://lore.kernel.org/qemu-riscv/20230702-eats-scorebook-c951f170d29f@spud/ [0] Link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/riscv/extensions.yaml [1] Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240124-unvarying-foothold-9dde2aaf95d4@spud> [ Changes by AF: - Rebase on recent changes ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-02-09hw/riscv/virt.c: use g_autofree in create_fdt_*Daniel Henrique Barboza
We have a lot of cases where a char or an uint32_t pointer is used once to alloc a string/array, read/written during the function, and then g_free() at the end. There's no pointer re-use - a single alloc, a single g_free(). Use 'g_autofree' to avoid the g_free() calls. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240122221529.86562-8-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-02-09hw/riscv/virt.c: use g_autofree in virt_machine_init()Daniel Henrique Barboza
Move 'soc_name' to the loop, and give it g_autofree, to avoid the manual g_free(). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240122221529.86562-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-02-09hw/riscv/virt.c: use g_autofree in create_fdt_virtio()Daniel Henrique Barboza
Put 'name' declaration inside the loop, with g_autofree, to avoid manually doing g_free() in each iteration. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240122221529.86562-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-02-09hw/riscv/virt.c: use g_autofree in create_fdt_sockets()Daniel Henrique Barboza
Move 'clust_name' inside the loop, and g_autofree, to avoid having to g_free() manually in each loop iteration. 'intc_phandles' is also g_autofreed to avoid another manual g_free(). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240122221529.86562-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-02-09hw/riscv/virt.c: use g_autofree in create_fdt_socket_cpus()Daniel Henrique Barboza
Move all char pointers to the loop. Use g_autofree in all of them to avoid the g_free() calls. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240122221529.86562-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-02-09hw/riscv/numa.c: use g_autofree in socket_fdt_write_distance_matrix()Daniel Henrique Barboza
Use g_autofree in 'dist_matrix' to avoid the manual g_free(). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240122221529.86562-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-02-09hw/riscv/virt-acpi-build.c: fix leak in build_rhct()Daniel Henrique Barboza
The 'isa' char pointer isn't being freed after use. Issue detected by Valgrind: ==38752== 128 bytes in 1 blocks are definitely lost in loss record 3,190 of 3,884 ==38752== at 0x484280F: malloc (vg_replace_malloc.c:442) ==38752== by 0x5189619: g_malloc (gmem.c:130) ==38752== by 0x51A5BF2: g_strconcat (gstrfuncs.c:628) ==38752== by 0x6C1E3E: riscv_isa_string_ext (cpu.c:2321) ==38752== by 0x6C1E3E: riscv_isa_string (cpu.c:2343) ==38752== by 0x6BD2EA: build_rhct (virt-acpi-build.c:232) ==38752== by 0x6BD2EA: virt_acpi_build (virt-acpi-build.c:556) ==38752== by 0x6BDC86: virt_acpi_setup (virt-acpi-build.c:662) ==38752== by 0x9C8DC6: notifier_list_notify (notify.c:39) ==38752== by 0x4A595A: qdev_machine_creation_done (machine.c:1589) ==38752== by 0x61E052: qemu_machine_creation_done (vl.c:2680) ==38752== by 0x61E052: qmp_x_exit_preconfig.part.0 (vl.c:2709) ==38752== by 0x6220C6: qmp_x_exit_preconfig (vl.c:2702) ==38752== by 0x6220C6: qemu_init (vl.c:3758) ==38752== by 0x425858: main (main.c:47) Fixes: ebfd392893 ("hw/riscv/virt: virt-acpi-build.c: Add RHCT Table") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240122221529.86562-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-02-09target/riscv: Move misa_mxl_max to classAkihiko Odaki
misa_mxl_max is common for all instances of a RISC-V CPU class so they are better put into class. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240203-riscv-v11-2-a23f4848a628@daynix.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-02-02hw/riscv: use qemu_configure_nic_device()David Woodhouse
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
2024-01-10target/riscv: add zicbop extension flagDaniel Henrique Barboza
QEMU already implements zicbom (Cache Block Management Operations) and zicboz (Cache Block Zero Operations). Commit 59cb29d6a5 ("target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder") added placeholders for what would be the instructions for zicbop (Cache Block Prefetch Operations), which are now no-ops. The RVA22U64 profile mandates zicbop, which means that applications that run with this profile might expect zicbop to be present in the riscv,isa DT and might behave badly if it's absent. Adding zicbop as an extension will make our future RVA22U64 implementation more in line with what userspace expects and, if/when cache block prefetch operations became relevant to QEMU, we already have the extension flag to turn then on/off as needed. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231218125334.37184-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-01-10hw/riscv/virt.c: fix the interrupts-extended property format of PLICYong-Xuan Wang
The interrupts-extended property of PLIC only has 2 * hart number fields when KVM enabled, copy 4 * hart number fields to fdt will expose some uninitialized value. In this patch, I also refactor the code about the setting of interrupts-extended property of PLIC for improved readability. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20231218090543.22353-1-yongxuan.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-01-10hw/riscv/virt-acpi-build.c: Add PLIC in MADTSunil V L
Add PLIC structures for each socket in the MADT when system is configured with PLIC as the external interrupt controller. Signed-off-by: Haibo Xu <haibo1.xu@intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20231218150247.466427-14-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-01-10hw/riscv/virt-acpi-build.c: Add IO controllers and devicesSunil V L
Add basic IO controllers and devices like PCI, VirtIO and UART in the ACPI namespace. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20231218150247.466427-13-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-01-10hw/riscv/virt: Update GPEX MMIO related propertiesSunil V L
Update the GPEX host bridge properties related to MMIO ranges with values set for the virt machine. Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20231218150247.466427-12-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-01-10hw/riscv/virt-acpi-build.c: Add MMU node in RHCTSunil V L
MMU type information is available via MMU node in RHCT. Add this node in RHCT. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20231218150247.466427-10-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-01-10hw/riscv/virt-acpi-build.c: Add CMO information in RHCTSunil V L
When CMO related extensions like Zicboz, Zicbom and Zicbop are enabled, the block size for those extensions need to be communicated via CMO node in RHCT. Add CMO node in RHCT if any of those CMO extensions are detected. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20231218150247.466427-9-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-01-10hw/riscv/virt-acpi-build.c: Add APLIC in the MADTSunil V L
Add APLIC structures for each socket in the MADT when system is configured with APLIC as the external wired interrupt controller. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20231218150247.466427-8-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-01-10hw/riscv/virt-acpi-build.c: Add IMSIC in the MADTSunil V L
Add IMSIC structure in MADT when IMSIC is configured. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20231218150247.466427-7-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-14 15:37:50 +0000