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AgeCommit message (Expand)Author
2021-10-28hw/riscv: opentitan: Fixup the PLIC context addressesAlistair Francis
2021-10-28hw/riscv: virt: Use the PLIC config helper functionAlistair Francis
2021-10-28hw/riscv: microchip_pfsoc: Use the PLIC config helper functionAlistair Francis
2021-10-28hw/riscv: sifive_u: Use the PLIC config helper functionAlistair Francis
2021-10-28hw/riscv: boot: Add a PLIC config string functionAlistair Francis
2021-10-28hw/riscv: virt: Don't use a macro for the PLIC configurationAlistair Francis
2021-10-22hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_idBin Meng
2021-10-22hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_idBin Meng
2021-10-22hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_idBin Meng
2021-10-22hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_idBin Meng
2021-10-22hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_idBin Meng
2021-10-22hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ra...Bin Meng
2021-10-22hw/riscv: opentitan: Update to the latest buildAlistair Francis
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson
2021-10-22hw/riscv: virt: Use machine->ram as the system memoryMingwang Li
2021-10-07hw/riscv: shakti_c: Mark as not user creatableAlistair Francis
2021-09-21hw/riscv: opentitan: Correct the USB Dev addressAlistair Francis
2021-09-21hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel
2021-09-21hw/riscv: virt: Re-factor FDT generationAnup Patel
2021-09-21hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel
2021-09-21hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel
2021-09-21sifive_u: Connect the SiFive PWM deviceAlistair Francis
2021-09-21hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO linesAlistair Francis
2021-09-21hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis
2021-09-21hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis
2021-09-01hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv()Peter Maydell
2021-09-01hw/riscv: virt: Move flash node to rootBin Meng
2021-09-01hw/char: Add config for shakti uartVijai Kumar K
2021-08-26arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell
2021-07-20hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machinesPhilippe Mathieu-Daudé
2021-07-15hw/riscv/boot: Check the error of fdt_pack()Alistair Francis
2021-07-15hw/riscv: opentitan: Add the flash aliasAlistair Francis
2021-07-15hw/riscv: opentitan: Add the unimplement rv_core_ibex_periAlistair Francis
2021-07-15hw/riscv: sifive_u: Make sure firmware info is 8-byte alignedBin Meng
2021-07-15hw/riscv: sifive_u: Correct the CLINT timebase frequencyBin Meng
2021-06-24hw/riscv: OpenTitan: Connect the mtime and mtimecmp timerAlistair Francis
2021-06-08hw/riscv: microchip_pfsoc: Support direct kernel bootBin Meng
2021-06-08hw/riscv: Use macros for BIOS image namesBin Meng
2021-06-08hw/riscv: Support the official PLIC DT bindingsBin Meng
2021-06-08hw/riscv: Support the official CLINT DT bindingsBin Meng
2021-06-08hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helperBin Meng
2021-06-08hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helperBin Meng
2021-05-11hw/riscv: Fix OT IBEX reset vectorAlexander Wagner
2021-05-11hw/riscv: Enable VIRTIO_VGA for RISC-V virt machineAlistair Francis
2021-05-11hw/opentitan: Update the interrupt layoutAlistair Francis
2021-05-11hw/riscv: Connect Shakti UART to Shakti platformVijai Kumar K
2021-05-11riscv: Add initial support for Shakti C machineVijai Kumar K
2021-05-11hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]Bin Meng
2021-05-02Do not include exec/address-spaces.h if it's not really necessaryThomas Huth
2021-05-02hw: Do not include qemu/log.h if it is not necessaryThomas Huth
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