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AgeCommit message (Expand)Author
2022-04-29hw/riscv: Enable TPM backendsAlistair Francis
2022-04-29hw/riscv: virt: Add device plug supportAlistair Francis
2022-04-29hw/riscv: virt: Add support for generating platform FDT entriesAlistair Francis
2022-04-29hw/riscv: virt: Create a platform busAlistair Francis
2022-04-29hw/riscv: virt: Add a machine done notifierAlistair Francis
2022-04-29hw/riscv: Don't add empty bootargs to device treeBin Meng
2022-04-29hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionallyBin Meng
2022-04-22hw/riscv: boot: Support 64bit fdt address.Dylan Jhong
2022-04-22hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabledNiklas Cassel
2022-04-22hw/riscv: virt: Exit if the user provided -bios in combination with KVMRalf Ramsauer
2022-04-22riscv: opentitan: Connect opentitan SPI HostWilfred Mallawa
2022-04-06Remove qemu-common.h include from most unitsMarc-André Lureau
2022-03-03hw: riscv: opentitan: fixup SPI addressesWilfred Mallawa
2022-03-03hw/riscv: virt: Increase maximum number of allowed CPUsAnup Patel
2022-03-03hw/riscv: virt: Add optional AIA IMSIC support to virt machineAnup Patel
2022-03-03hw/riscv: virt: Add optional AIA APLIC support to virt machineAnup Patel
2022-02-16hw/riscv: virt: Use AIA INTC compatible string when availableAnup Patel
2022-01-21hw/riscv: Remove macros for ELF BIOS image namesAnup Patel
2022-01-21hw/riscv: spike: Allow using binary firmware as biosAnup Patel
2022-01-21target/riscv: Support start kernel directly by KVMYifei Jiang
2022-01-21riscv: opentitan: fixup plic stride lenWilfred Mallawa
2022-01-08hw/riscv: Use error_fatal for SoC realisationAlistair Francis
2021-12-20hw/riscv: Use load address rather than entry point for fw_dynamic next_addrJessica Clarke
2021-12-15hw: Replace trivial drive_get_next() by drive_get()Markus Armbruster
2021-12-15hw/sd/ssi-sd: Do not create SD card within controller's realizeMarkus Armbruster
2021-10-28hw/riscv: opentitan: Fixup the PLIC context addressesAlistair Francis
2021-10-28hw/riscv: virt: Use the PLIC config helper functionAlistair Francis
2021-10-28hw/riscv: microchip_pfsoc: Use the PLIC config helper functionAlistair Francis
2021-10-28hw/riscv: sifive_u: Use the PLIC config helper functionAlistair Francis
2021-10-28hw/riscv: boot: Add a PLIC config string functionAlistair Francis
2021-10-28hw/riscv: virt: Don't use a macro for the PLIC configurationAlistair Francis
2021-10-22hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_idBin Meng
2021-10-22hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_idBin Meng
2021-10-22hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_idBin Meng
2021-10-22hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_idBin Meng
2021-10-22hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_idBin Meng
2021-10-22hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ra...Bin Meng
2021-10-22hw/riscv: opentitan: Update to the latest buildAlistair Francis
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson
2021-10-22hw/riscv: virt: Use machine->ram as the system memoryMingwang Li
2021-10-07hw/riscv: shakti_c: Mark as not user creatableAlistair Francis
2021-09-21hw/riscv: opentitan: Correct the USB Dev addressAlistair Francis
2021-09-21hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel
2021-09-21hw/riscv: virt: Re-factor FDT generationAnup Patel
2021-09-21hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel
2021-09-21hw/intc: Rename sifive_clint sources to riscv_aclint sourcesAnup Patel
2021-09-21sifive_u: Connect the SiFive PWM deviceAlistair Francis
2021-09-21hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO linesAlistair Francis
2021-09-21hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis
2021-09-21hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis
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