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AgeCommit message (Expand)Author
2020-06-03riscv: Initial commit of OpenTitan machineAlistair Francis
2020-06-03riscv: sifive_e: Manually define the machineAlistair Francis
2020-06-03hw/riscv: spike: Remove deprecated ISA specific machinesAlistair Francis
2020-06-03hw/riscv: virt: Remove the riscv_ prefix of the machine* functionsBin Meng
2020-06-03hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functionsBin Meng
2020-06-03riscv: Change the default behavior if no -bios option is specifiedBin Meng
2020-06-03riscv: Suppress the error report for QEMU testing with riscv_find_firmware()Bin Meng
2020-05-18hw: Use QEMU_IS_ALIGNED() on parallel flash block sizePhilippe Mathieu-Daudé
2020-05-15qom: Drop parameter @errp of object_property_add() & friendsMarkus Armbruster
2020-05-15qom: Drop object_property_set_description() parameter @errpMarkus Armbruster
2020-04-29hw/riscv/spike: Allow more than one CPUsAnup Patel
2020-04-29hw/riscv/spike: Allow loading firmware separately using -bios optionAnup Patel
2020-04-29hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()Anup Patel
2020-04-29riscv: sifive_e: Support changing CPU typeCorey Wharton
2020-04-29hw/riscv: Generate correct "mmu-type" for 32-bit machinesBin Meng
2020-04-29riscv/sifive_u: Add a serial property to the sifive_u machineBin Meng
2020-04-29riscv/sifive_u: Add a serial property to the sifive_u SoCAlistair Francis
2020-04-29riscv/sifive_u: Fix up file orderingAlistair Francis
2020-04-29various: Remove suspicious '\' character outside of #define in C codePhilippe Mathieu-Daudé
2020-03-17Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
2020-03-17hw/riscv: Let devices own the MemoryRegion they createPhilippe Mathieu-Daudé
2020-03-17hw/riscv: Use memory_region_init_rom() with read-only regionsPhilippe Mathieu-Daudé
2020-03-16riscv: sifive_u: Update BIOS_FILENAME for 32-bitBin Meng
2020-03-03Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf3' i...Peter Maydell
2020-02-28hw: Make MachineClass::is_default a boolean typePhilippe Mathieu-Daudé
2020-02-27hw/riscv: Provide rdtime callback for TCG in CLINT emulationAnup Patel
2020-02-27riscv: virt: Allow PCI address 0Bin Meng
2020-02-10riscv: virt: Use Goldfish RTC deviceAnup Patel
2020-02-10riscv/virt: Add syscon reboot and poweroff DT nodesAnup Patel
2020-01-29hw/core/loader: Let load_elf() populate a field with CPU-specific flagsAleksandar Markovic
2020-01-27Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
2020-01-24qdev: set properties with device_class_set_props()Marc-André Lureau
2020-01-16riscv/sifive_u: fix a memory leak in soc_realize()Pan Nengyuan
2020-01-08chardev: Use QEMUChrEvent enum in IOEventHandler typedefPhilippe Mathieu-Daudé
2019-11-25hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()Zhuang, Siwei (Data61, Kensington NSW)
2019-11-25RISC-V: virt: This is a "sifive,test1" test finisherPalmer Dabbelt
2019-11-14riscv/virt: Increase flash sizeAlistair Francis
2019-10-28riscv/boot: Fix possible memory leakAlistair Francis
2019-10-28riscv/virt: Jump to pflash if specifiedAlistair Francis
2019-10-28riscv/virt: Add the PFlash CFI01 deviceAlistair Francis
2019-10-28riscv/virt: Manually define the machineAlistair Francis
2019-10-28riscv/sifive_u: Add the start-in-flash propertyAlistair Francis
2019-10-28riscv/sifive_u: Manually define the machineAlistair Francis
2019-10-28riscv/sifive_u: Add QSPI memory regionAlistair Francis
2019-10-28riscv/sifive_u: Add L2-LIM cache memoryAlistair Francis
2019-10-28riscv: sifive_u: Add ethernet0 to the aliases nodeBin Meng
2019-10-28riscv: hw: Drop "clock-frequency" property of cpu nodesBin Meng
2019-09-17riscv: sifive_u: Update model and compatible strings in device treeBin Meng
2019-09-17riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernetBin Meng
2019-09-17riscv: sifive_u: Fix broken GEM supportBin Meng