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AgeCommit message (Expand)Author
2020-09-09hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng
2020-09-09hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng
2020-09-09hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng
2020-09-09hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng
2020-09-09hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng
2020-09-09target/riscv: cpu: Set reset vector based on the configured property valueBin Meng
2020-09-09hw/riscv: hart: Add a new 'resetvec' propertyBin Meng
2020-09-09riscv: sifive_test: Allow 16-bit writes to memory regionNathan Chancellor
2020-09-08configure: do not include dependency flags in QEMU_CFLAGS and LIBSPaolo Bonzini
2020-08-27opentitan: Rename memmap enum constantsEduardo Habkost
2020-08-25hw/riscv: virt: Allow creating multiple NUMA socketsAnup Patel
2020-08-25hw/riscv: spike: Allow creating multiple NUMA socketsAnup Patel
2020-08-25hw/riscv: Add helpers for RISC-V multi-socket NUMA machinesAnup Patel
2020-08-25hw/riscv: Allow creating multiple instances of PLICAnup Patel
2020-08-25hw/riscv: Allow creating multiple instances of CLINTAnup Patel
2020-08-21hw/riscv: spike: Change the default bios to use generic platform imageBin Meng
2020-08-21hw/riscv: Use pre-built bios image of generic platform for virt & sifive_uBin Meng
2020-08-21hw/riscv: sifive_u: Add a dummy L2 cache controller deviceBin Meng
2020-08-21meson: convert hw/arch*Marc-André Lureau
2020-08-21trace: switch position of headers to what Meson requiresPaolo Bonzini
2020-07-22hw/riscv: sifive_e: Correct debug block sizeBin Meng
2020-07-21hw: Mark nd_table[] misuse in realize methods FIXMEMarkus Armbruster
2020-07-13hw/riscv: Modify MROM size to end at 0x10000Bin Meng
2020-07-13RISC-V: Support 64 bit start addressAtish Patra
2020-07-13riscv: Add opensbi firmware dynamic supportAtish Patra
2020-07-13RISC-V: Copy the fdt in dram instead of ROMAtish Patra
2020-07-13riscv: Unify Qemu's reset vector code pathAtish Patra
2020-07-13hw/riscv: virt: Sort the SoC memmap table entriesBin Meng
2020-07-10error: Eliminate error_propagate() with Coccinelle, part 1Markus Armbruster
2020-07-10qom: Put name parameter before value / visitor parameterMarkus Armbruster
2020-07-10qdev: Use returned bool to check for qdev_realize() etc. failureMarkus Armbruster
2020-07-02hw/riscv: Allow 64 bit access to SiFive CLINTAlistair Francis
2020-07-02riscv: plic: Add a couple of mising sifive_plic_update callsJessica Clarke
2020-07-02riscv: plic: Honour source prioritiesJessica Clarke
2020-07-02riscv_hart: Fix riscv_harts_realize() error API violationsMarkus Armbruster
2020-07-02riscv/sifive_u: Fix sifive_u_soc_realize() error API violationsMarkus Armbruster
2020-06-19hw/riscv: sifive_u: Add a dummy DDR memory controller deviceBin Meng
2020-06-19hw/riscv: sifive_u: Sort the SoC memmap table entriesBin Meng
2020-06-19hw/riscv: sifive_u: Support different boot source per MSEL pin stateBin Meng
2020-06-19hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng
2020-06-19hw/riscv: sifive_u: Add a new property msel for MSEL pin stateBin Meng
2020-06-19hw/riscv: sifive_u: Rename serial property get/set functions to a generic nameBin Meng
2020-06-19hw/riscv: sifive_u: Add reset functionalityBin Meng
2020-06-19hw/riscv: sifive_gpio: Do not blindly trigger output IRQsBin Meng
2020-06-19hw/riscv: sifive_u: Hook a GPIO controllerBin Meng
2020-06-19hw/riscv: sifive_gpio: Add a new 'ngpio' propertyBin Meng
2020-06-19hw/riscv: sifive_gpio: Clean up the codesBin Meng
2020-06-19hw/riscv: sifive_u: Generate device tree node for OTPBin Meng
2020-06-19hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bitBin Meng
2020-06-19hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng
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