Age | Commit message (Expand) | Author |
2021-05-02 | Do not include exec/address-spaces.h if it's not really necessary | Thomas Huth |
2021-05-02 | hw: Do not include qemu/log.h if it is not necessary | Thomas Huth |
2021-05-02 | hw: Do not include hw/irq.h if it is not necessary | Thomas Huth |
2021-03-22 | hw/riscv: microchip_pfsoc: Map EMMC/SD mux register | Bin Meng |
2021-03-22 | hw/riscv: allow ramfb on virt | Asherah Connor |
2021-03-22 | hw/riscv: Add fw_cfg support to virt | Asherah Connor |
2021-03-11 | Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-docs-xen-upda... | Peter Maydell |
2021-03-10 | hw/riscv: migrate fdt field to generic MachineState | Alex Bennée |
2021-03-09 | qtest: delete superfluous inclusions of qtest.h | Chen Qun |
2021-03-04 | hw/riscv: virt: Map high mmio for PCIe | Bin Meng |
2021-03-04 | hw/riscv: virt: Limit RAM size in a 32-bit system | Bin Meng |
2021-03-04 | hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() | Bin Meng |
2021-03-04 | hw/riscv: Drop 'struct MemmapEntry' | Bin Meng |
2021-03-04 | hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card | Bin Meng |
2021-03-04 | hw/riscv: sifive_u: Add QSPI0 controller and connect a flash | Bin Meng |
2021-01-16 | riscv: Pass RISCVHartArrayState by pointer | Alistair Francis |
2021-01-16 | hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type | Bin Meng |
2021-01-16 | RISC-V: Place DTB at 3GB boundary instead of 4GB | Atish Patra |
2020-12-17 | riscv/opentitan: Update the OpenTitan memory layout | Alistair Francis |
2020-12-17 | hw/riscv: Use the CPU to determine if 32-bit | Alistair Francis |
2020-12-17 | hw/riscv: sifive_u: Remove compile time XLEN checks | Alistair Francis |
2020-12-17 | hw/riscv: spike: Remove compile time XLEN checks | Alistair Francis |
2020-12-17 | hw/riscv: virt: Remove compile time XLEN checks | Alistair Francis |
2020-12-17 | hw/riscv: boot: Remove compile time XLEN checks | Alistair Francis |
2020-12-17 | riscv: virt: Remove target macro conditionals | Alistair Francis |
2020-12-17 | riscv: spike: Remove target macro conditionals | Alistair Francis |
2020-12-17 | hw/riscv: Expand the is 32-bit check to support more CPUs | Alistair Francis |
2020-12-17 | hw/riscv: microchip_pfsoc: add QSPI NOR flash | Vitaly Wool |
2020-12-17 | hw/riscv: sifive_u: Add UART1 DT node in the generated DTB | Anup Patel |
2020-12-15 | vl: make qemu_get_machine_opts static | Paolo Bonzini |
2020-12-10 | vl: extract softmmu/datadir.c | Paolo Bonzini |
2020-12-10 | riscv: do not use ram_size global | Paolo Bonzini |
2020-11-03 | hw/riscv: microchip_pfsoc: Hook the I2C1 controller | Bin Meng |
2020-11-03 | hw/riscv: microchip_pfsoc: Correct DDR memory map | Bin Meng |
2020-11-03 | hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 | Bin Meng |
2020-11-03 | hw/riscv: microchip_pfsoc: Connect the SYSREG module | Bin Meng |
2020-11-03 | hw/riscv: microchip_pfsoc: Connect the IOSCB module | Bin Meng |
2020-11-03 | hw/riscv: microchip_pfsoc: Connect DDR memory controller modules | Bin Meng |
2020-11-03 | hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps | Bin Meng |
2020-11-03 | hw/riscv: virt: Allow passing custom DTB | Anup Patel |
2020-11-03 | hw/riscv: sifive_u: Allow passing custom DTB | Anup Patel |
2020-10-22 | hw/riscv: Load the kernel after the firmware | Alistair Francis |
2020-10-22 | hw/riscv: Add a riscv_is_32_bit() function | Alistair Francis |
2020-10-22 | hw/riscv: Return the end address of the loaded firmware | Alistair Francis |
2020-10-22 | hw/riscv: sifive_u: Allow specifying the CPU | Alistair Francis |
2020-09-25 | load_elf: Remove unused address variables from callers | BALATON Zoltan |
2020-09-22 | sifive_u: Register "start-in-flash" as class property | Eduardo Habkost |
2020-09-22 | sifive_e: Register "revb" as class property | Eduardo Habkost |
2020-09-18 | sifive_u: Rename memmap enum constants | Eduardo Habkost |
2020-09-18 | sifive_e: Rename memmap enum constants | Eduardo Habkost |