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AgeCommit message (Expand)Author
2021-03-11Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-docs-xen-upda...Peter Maydell
2021-03-10hw/riscv: migrate fdt field to generic MachineStateAlex Bennée
2021-03-09qtest: delete superfluous inclusions of qtest.hChen Qun
2021-03-04hw/riscv: virt: Map high mmio for PCIeBin Meng
2021-03-04hw/riscv: virt: Limit RAM size in a 32-bit systemBin Meng
2021-03-04hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()Bin Meng
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng
2021-03-04hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng
2021-03-04hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng
2021-01-16riscv: Pass RISCVHartArrayState by pointerAlistair Francis
2021-01-16hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_typeBin Meng
2021-01-16RISC-V: Place DTB at 3GB boundary instead of 4GBAtish Patra
2020-12-17riscv/opentitan: Update the OpenTitan memory layoutAlistair Francis
2020-12-17hw/riscv: Use the CPU to determine if 32-bitAlistair Francis
2020-12-17hw/riscv: sifive_u: Remove compile time XLEN checksAlistair Francis
2020-12-17hw/riscv: spike: Remove compile time XLEN checksAlistair Francis
2020-12-17hw/riscv: virt: Remove compile time XLEN checksAlistair Francis
2020-12-17hw/riscv: boot: Remove compile time XLEN checksAlistair Francis
2020-12-17riscv: virt: Remove target macro conditionalsAlistair Francis
2020-12-17riscv: spike: Remove target macro conditionalsAlistair Francis
2020-12-17hw/riscv: Expand the is 32-bit check to support more CPUsAlistair Francis
2020-12-17hw/riscv: microchip_pfsoc: add QSPI NOR flashVitaly Wool
2020-12-17hw/riscv: sifive_u: Add UART1 DT node in the generated DTBAnup Patel
2020-12-15vl: make qemu_get_machine_opts staticPaolo Bonzini
2020-12-10vl: extract softmmu/datadir.cPaolo Bonzini
2020-12-10riscv: do not use ram_size globalPaolo Bonzini
2020-11-03hw/riscv: microchip_pfsoc: Hook the I2C1 controllerBin Meng
2020-11-03hw/riscv: microchip_pfsoc: Correct DDR memory mapBin Meng
2020-11-03hw/riscv: microchip_pfsoc: Map the reserved memory at address 0Bin Meng
2020-11-03hw/riscv: microchip_pfsoc: Connect the SYSREG moduleBin Meng
2020-11-03hw/riscv: microchip_pfsoc: Connect the IOSCB moduleBin Meng
2020-11-03hw/riscv: microchip_pfsoc: Connect DDR memory controller modulesBin Meng
2020-11-03hw/riscv: microchip_pfsoc: Document where to look at the SoC memory mapsBin Meng
2020-11-03hw/riscv: virt: Allow passing custom DTBAnup Patel
2020-11-03hw/riscv: sifive_u: Allow passing custom DTBAnup Patel
2020-10-22hw/riscv: Load the kernel after the firmwareAlistair Francis
2020-10-22hw/riscv: Add a riscv_is_32_bit() functionAlistair Francis
2020-10-22hw/riscv: Return the end address of the loaded firmwareAlistair Francis
2020-10-22hw/riscv: sifive_u: Allow specifying the CPUAlistair Francis
2020-09-25load_elf: Remove unused address variables from callersBALATON Zoltan
2020-09-22sifive_u: Register "start-in-flash" as class propertyEduardo Habkost
2020-09-22sifive_e: Register "revb" as class propertyEduardo Habkost
2020-09-18sifive_u: Rename memmap enum constantsEduardo Habkost
2020-09-18sifive_e: Rename memmap enum constantsEduardo Habkost
2020-09-09hw/riscv: Sort the Kconfig options in alphabetical orderBin Meng
2020-09-09hw/riscv: Drop CONFIG_SIFIVEBin Meng
2020-09-09hw/riscv: Always build riscv_hart.cBin Meng
2020-09-09hw/riscv: Move sifive_test model to hw/miscBin Meng
2020-09-09hw/riscv: Move sifive_uart model to hw/charBin Meng
2020-09-09hw/riscv: Move riscv_htif model to hw/charBin Meng
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