Age | Commit message (Expand) | Author |
2022-10-17 | hw/riscv: set machine->fdt in spike_board_init() | Daniel Henrique Barboza |
2022-10-17 | hw/riscv: set machine->fdt in sifive_u_machine_init() | Daniel Henrique Barboza |
2022-10-14 | hw/riscv: virt: Enable booting S-mode firmware from pflash | Sunil V L |
2022-10-14 | hw/riscv: virt: Move create_fw_cfg() prior to loading kernel | Sunil V L |
2022-10-14 | hw/riscv: Update comment for qtest check in riscv_find_firmware() | Bin Meng |
2022-09-27 | hw/riscv: opentitan: Expose the resetvec as a SoC property | Alistair Francis |
2022-09-27 | hw/riscv: opentitan: Fixup resetvec | Alistair Francis |
2022-09-07 | hw/riscv: virt: Add PMU DT node to the device tree | Atish Patra |
2022-09-07 | target/riscv: Use official extension names for AIA CSRs | Anup Patel |
2022-09-07 | hw/riscv: virt: fix syscon subnode paths | Conor Dooley |
2022-09-07 | hw/riscv: virt: fix the plic's address cells | Conor Dooley |
2022-09-07 | hw/riscv: virt: fix uart node name | Conor Dooley |
2022-09-07 | hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals | Conor Dooley |
2022-09-07 | hw/riscv: opentitan: bump opentitan version | Wilfred Mallawa |
2022-09-07 | hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec() | Daniel Henrique Barboza |
2022-09-07 | hw/riscv: virt: pass random seed to fdt | Jason A. Donenfeld |
2022-07-03 | hw/riscv: boot: Reduce FDT address alignment constraints | Alistair Francis |
2022-06-10 | hw/core/loader: return image sizes as ssize_t | Jamie Iles |
2022-06-10 | hw/riscv: virt: Generate fw_cfg DT node correctly | Atish Patra |
2022-05-24 | hw/riscv: virt: Fix interrupt parent for dynamic platform devices | Anup Patel |
2022-05-24 | hw/riscv/sifive_u: Resolve redundant property accessors | Bernhard Beschow |
2022-05-24 | hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan) | Tsukasa OI |
2022-05-24 | hw/riscv: Make CPU config error handling generous (virt/spike) | Tsukasa OI |
2022-04-29 | hw/riscv: Enable TPM backends | Alistair Francis |
2022-04-29 | hw/riscv: virt: Add device plug support | Alistair Francis |
2022-04-29 | hw/riscv: virt: Add support for generating platform FDT entries | Alistair Francis |
2022-04-29 | hw/riscv: virt: Create a platform bus | Alistair Francis |
2022-04-29 | hw/riscv: virt: Add a machine done notifier | Alistair Francis |
2022-04-29 | hw/riscv: Don't add empty bootargs to device tree | Bin Meng |
2022-04-29 | hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionally | Bin Meng |
2022-04-22 | hw/riscv: boot: Support 64bit fdt address. | Dylan Jhong |
2022-04-22 | hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled | Niklas Cassel |
2022-04-22 | hw/riscv: virt: Exit if the user provided -bios in combination with KVM | Ralf Ramsauer |
2022-04-22 | riscv: opentitan: Connect opentitan SPI Host | Wilfred Mallawa |
2022-04-06 | Remove qemu-common.h include from most units | Marc-André Lureau |
2022-03-03 | hw: riscv: opentitan: fixup SPI addresses | Wilfred Mallawa |
2022-03-03 | hw/riscv: virt: Increase maximum number of allowed CPUs | Anup Patel |
2022-03-03 | hw/riscv: virt: Add optional AIA IMSIC support to virt machine | Anup Patel |
2022-03-03 | hw/riscv: virt: Add optional AIA APLIC support to virt machine | Anup Patel |
2022-02-16 | hw/riscv: virt: Use AIA INTC compatible string when available | Anup Patel |
2022-01-21 | hw/riscv: Remove macros for ELF BIOS image names | Anup Patel |
2022-01-21 | hw/riscv: spike: Allow using binary firmware as bios | Anup Patel |
2022-01-21 | target/riscv: Support start kernel directly by KVM | Yifei Jiang |
2022-01-21 | riscv: opentitan: fixup plic stride len | Wilfred Mallawa |
2022-01-08 | hw/riscv: Use error_fatal for SoC realisation | Alistair Francis |
2021-12-20 | hw/riscv: Use load address rather than entry point for fw_dynamic next_addr | Jessica Clarke |
2021-12-15 | hw: Replace trivial drive_get_next() by drive_get() | Markus Armbruster |
2021-12-15 | hw/sd/ssi-sd: Do not create SD card within controller's realize | Markus Armbruster |
2021-10-28 | hw/riscv: opentitan: Fixup the PLIC context addresses | Alistair Francis |
2021-10-28 | hw/riscv: virt: Use the PLIC config helper function | Alistair Francis |