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QEMU is a generic and open source machine & userspace emulator and virtualizer
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2020-07-22
hw/riscv: sifive_e: Correct debug block size
Bin Meng
2020-07-21
hw: Mark nd_table[] misuse in realize methods FIXME
Markus Armbruster
2020-07-13
hw/riscv: Modify MROM size to end at 0x10000
Bin Meng
2020-07-13
RISC-V: Support 64 bit start address
Atish Patra
2020-07-13
riscv: Add opensbi firmware dynamic support
Atish Patra
2020-07-13
RISC-V: Copy the fdt in dram instead of ROM
Atish Patra
2020-07-13
riscv: Unify Qemu's reset vector code path
Atish Patra
2020-07-13
hw/riscv: virt: Sort the SoC memmap table entries
Bin Meng
2020-07-10
error: Eliminate error_propagate() with Coccinelle, part 1
Markus Armbruster
2020-07-10
qom: Put name parameter before value / visitor parameter
Markus Armbruster
2020-07-10
qdev: Use returned bool to check for qdev_realize() etc. failure
Markus Armbruster
2020-07-02
hw/riscv: Allow 64 bit access to SiFive CLINT
Alistair Francis
2020-07-02
riscv: plic: Add a couple of mising sifive_plic_update calls
Jessica Clarke
2020-07-02
riscv: plic: Honour source priorities
Jessica Clarke
2020-07-02
riscv_hart: Fix riscv_harts_realize() error API violations
Markus Armbruster
2020-07-02
riscv/sifive_u: Fix sifive_u_soc_realize() error API violations
Markus Armbruster
2020-06-19
hw/riscv: sifive_u: Add a dummy DDR memory controller device
Bin Meng
2020-06-19
hw/riscv: sifive_u: Sort the SoC memmap table entries
Bin Meng
2020-06-19
hw/riscv: sifive_u: Support different boot source per MSEL pin state
Bin Meng
2020-06-19
hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
Bin Meng
2020-06-19
hw/riscv: sifive_u: Add a new property msel for MSEL pin state
Bin Meng
2020-06-19
hw/riscv: sifive_u: Rename serial property get/set functions to a generic name
Bin Meng
2020-06-19
hw/riscv: sifive_u: Add reset functionality
Bin Meng
2020-06-19
hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
Bin Meng
2020-06-19
hw/riscv: sifive_u: Hook a GPIO controller
Bin Meng
2020-06-19
hw/riscv: sifive_gpio: Add a new 'ngpio' property
Bin Meng
2020-06-19
hw/riscv: sifive_gpio: Clean up the codes
Bin Meng
2020-06-19
hw/riscv: sifive_u: Generate device tree node for OTP
Bin Meng
2020-06-19
hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit
Bin Meng
2020-06-19
hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions
Bin Meng
2020-06-19
hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions
Bin Meng
2020-06-19
riscv/opentitan: Connect the UART device
Alistair Francis
2020-06-19
riscv/opentitan: Connect the PLIC device
Alistair Francis
2020-06-19
hw/char: Initial commit of Ibex UART
Alistair Francis
2020-06-19
riscv/opentitan: Fix the ROM size
Alistair Francis
2020-06-19
sifive_e: Support the revB machine
Alistair Francis
2020-06-15
qdev: Convert bus-less devices to qdev_realize() with Coccinelle
Markus Armbruster
2020-06-15
sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2
Markus Armbruster
2020-06-15
sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1
Markus Armbruster
2020-06-15
sysbus: Convert to sysbus_realize() etc. with Coccinelle
Markus Armbruster
2020-06-15
qom: Less verbose object_initialize_child()
Markus Armbruster
2020-06-15
qom: Tidy up a few object_initialize_child() calls
Markus Armbruster
2020-06-15
qdev: Convert uses of qdev_create() manually
Markus Armbruster
2020-06-15
qdev: Convert uses of qdev_create() with Coccinelle
Markus Armbruster
2020-06-15
riscv: Fix to put "riscv.hart_array" devices on sysbus
Markus Armbruster
2020-06-03
riscv: Initial commit of OpenTitan machine
Alistair Francis
2020-06-03
riscv: sifive_e: Manually define the machine
Alistair Francis
2020-06-03
hw/riscv: spike: Remove deprecated ISA specific machines
Alistair Francis
2020-06-03
hw/riscv: virt: Remove the riscv_ prefix of the machine* functions
Bin Meng
2020-06-03
hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions
Bin Meng
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