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AgeCommit message (Expand)Author
2020-07-22hw/riscv: sifive_e: Correct debug block sizeBin Meng
2020-07-21hw: Mark nd_table[] misuse in realize methods FIXMEMarkus Armbruster
2020-07-13hw/riscv: Modify MROM size to end at 0x10000Bin Meng
2020-07-13RISC-V: Support 64 bit start addressAtish Patra
2020-07-13riscv: Add opensbi firmware dynamic supportAtish Patra
2020-07-13RISC-V: Copy the fdt in dram instead of ROMAtish Patra
2020-07-13riscv: Unify Qemu's reset vector code pathAtish Patra
2020-07-13hw/riscv: virt: Sort the SoC memmap table entriesBin Meng
2020-07-10error: Eliminate error_propagate() with Coccinelle, part 1Markus Armbruster
2020-07-10qom: Put name parameter before value / visitor parameterMarkus Armbruster
2020-07-10qdev: Use returned bool to check for qdev_realize() etc. failureMarkus Armbruster
2020-07-02hw/riscv: Allow 64 bit access to SiFive CLINTAlistair Francis
2020-07-02riscv: plic: Add a couple of mising sifive_plic_update callsJessica Clarke
2020-07-02riscv: plic: Honour source prioritiesJessica Clarke
2020-07-02riscv_hart: Fix riscv_harts_realize() error API violationsMarkus Armbruster
2020-07-02riscv/sifive_u: Fix sifive_u_soc_realize() error API violationsMarkus Armbruster
2020-06-19hw/riscv: sifive_u: Add a dummy DDR memory controller deviceBin Meng
2020-06-19hw/riscv: sifive_u: Sort the SoC memmap table entriesBin Meng
2020-06-19hw/riscv: sifive_u: Support different boot source per MSEL pin stateBin Meng
2020-06-19hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng
2020-06-19hw/riscv: sifive_u: Add a new property msel for MSEL pin stateBin Meng
2020-06-19hw/riscv: sifive_u: Rename serial property get/set functions to a generic nameBin Meng
2020-06-19hw/riscv: sifive_u: Add reset functionalityBin Meng
2020-06-19hw/riscv: sifive_gpio: Do not blindly trigger output IRQsBin Meng
2020-06-19hw/riscv: sifive_u: Hook a GPIO controllerBin Meng
2020-06-19hw/riscv: sifive_gpio: Add a new 'ngpio' propertyBin Meng
2020-06-19hw/riscv: sifive_gpio: Clean up the codesBin Meng
2020-06-19hw/riscv: sifive_u: Generate device tree node for OTPBin Meng
2020-06-19hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bitBin Meng
2020-06-19hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng
2020-06-19hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng
2020-06-19riscv/opentitan: Connect the UART deviceAlistair Francis
2020-06-19riscv/opentitan: Connect the PLIC deviceAlistair Francis
2020-06-19hw/char: Initial commit of Ibex UARTAlistair Francis
2020-06-19riscv/opentitan: Fix the ROM sizeAlistair Francis
2020-06-19sifive_e: Support the revB machineAlistair Francis
2020-06-15qdev: Convert bus-less devices to qdev_realize() with CoccinelleMarkus Armbruster
2020-06-15sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2Markus Armbruster
2020-06-15sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1Markus Armbruster
2020-06-15sysbus: Convert to sysbus_realize() etc. with CoccinelleMarkus Armbruster
2020-06-15qom: Less verbose object_initialize_child()Markus Armbruster
2020-06-15qom: Tidy up a few object_initialize_child() callsMarkus Armbruster
2020-06-15qdev: Convert uses of qdev_create() manuallyMarkus Armbruster
2020-06-15qdev: Convert uses of qdev_create() with CoccinelleMarkus Armbruster
2020-06-15riscv: Fix to put "riscv.hart_array" devices on sysbusMarkus Armbruster
2020-06-03riscv: Initial commit of OpenTitan machineAlistair Francis
2020-06-03riscv: sifive_e: Manually define the machineAlistair Francis
2020-06-03hw/riscv: spike: Remove deprecated ISA specific machinesAlistair Francis
2020-06-03hw/riscv: virt: Remove the riscv_ prefix of the machine* functionsBin Meng
2020-06-03hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functionsBin Meng