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QEMU is a generic and open source machine & userspace emulator and virtualizer
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riscv
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2019-09-17
riscv: Add a helper routine for finding firmware
Bin Meng
2019-09-17
riscv: plic: Remove unused interrupt functions
Alistair Francis
2019-09-17
riscv: sifive_u: Fix clock-names property for ethernet node
Guenter Roeck
2019-09-17
riscv: sivive_u: Add dummy serial clock and aliases entry for uart
Guenter Roeck
2019-09-17
riscv: sifive_u: Add support for loading initrd
Guenter Roeck
2019-08-16
Include sysemu/sysemu.h a lot less
Markus Armbruster
2019-08-16
Include hw/boards.h a bit less
Markus Armbruster
2019-08-16
Include hw/qdev-properties.h less
Markus Armbruster
2019-08-16
Include hw/hw.h exactly where needed
Markus Armbruster
2019-08-16
Include migration/vmstate.h less
Markus Armbruster
2019-08-16
Include hw/irq.h a lot less
Markus Armbruster
2019-08-16
Include sysemu/reset.h a lot less
Markus Armbruster
2019-07-26
riscv/boot: Fixup the RISC-V firmware warning
Alistair Francis
2019-07-18
hw/riscv: Load OpenSBI as the default firmware
Alistair Francis
2019-07-05
hw/riscv: Replace global smp variables with machine smp properties
Like Xu
2019-06-27
hw/riscv: Extend the kernel loading support
Alistair Francis
2019-06-27
hw/riscv: Add support for loading a firmware
Alistair Francis
2019-06-27
hw/riscv: Split out the boot functions
Alistair Francis
2019-06-27
riscv: sifive_u: Update the plic hart config to support multicore
Bin Meng
2019-06-27
riscv: sifive_u: Do not create hard-coded phandles in DT
Bin Meng
2019-06-25
riscv: virt: Add cpu-topology DT node.
Atish Patra
2019-06-23
RISC-V: Fix a memory leak when realizing a sifive_e
Palmer Dabbelt
2019-06-23
riscv: virt: Correct pci "bus-range" encoding
Bin Meng
2019-06-23
sifive_prci: Read and write PRCI registers
Nathaniel Graff
2019-06-12
Include qemu/module.h where needed, drop it from qemu-common.h
Markus Armbruster
2019-05-24
riscv: spike: Add a generic spike machine
Alistair Francis
2019-05-24
riscv: virt: Allow specifying a CPU via commandline
Alistair Francis
2019-05-24
target/riscv: Remove unused include of riscv_htif.h for virt board riscv
Jonathan Behrens
2019-05-24
SiFive RISC-V GPIO Device
Fabien Chouteau
2019-04-04
riscv: plic: Log guest errors
Alistair Francis
2019-04-04
riscv: plic: Fix incorrect irq calculation
Alistair Francis
2019-03-28
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
Peter Maydell
2019-03-19
riscv: sifive_u: Correct UART0's IRQ in the device tree
Bin Meng
2019-03-19
riscv: sifive_uart: Generate TX interrupt
Bin Meng
2019-03-19
riscv: sifive_u: Allow up to 4 CPUs to be created
Alistair Francis
2019-03-19
RISC-V: Allow interrupt controllers to claim interrupts
Michael Clark
2019-03-19
RISC-V: Replace __builtin_popcount with ctpop8 in PLIC
Michael Clark
2019-03-18
kconfig: add CONFIG_MSI_NONBROKEN
Paolo Bonzini
2019-03-18
riscv: plic: Set msi_nonbroken as true
Alistair Francis
2019-03-11
riscv/Kconfig: enable PCI_DEVICES
David Abdurachmanov
2019-03-07
riscv-softmmu.mak: replace CONFIG_* with Kconfig "select" directives
Paolo Bonzini
2019-03-07
kconfig: introduce kconfig files
Paolo Bonzini
2019-02-11
riscv: Ensure the kernel start address is correctly cast
Alistair Francis
2019-02-05
hw/riscv/Makefile.objs: Create CONFIG_* for riscv boards
Yang Zhong
2019-02-05
elf: Add optional function ptr to load_elf() to parse ELF notes
Liam Merwick
2018-12-20
sifive_uart: Implement interrupt pending register
Nathaniel Graff
2018-12-20
RISC-V: Enable second UART on sifive_e and sifive_u
Michael Clark
2018-12-20
RISC-V: Fix PLIC pending bitfield reads
Michael Clark
2018-12-20
RISC-V: Fix CLINT timecmp low 32-bit writes
Michael Clark
2018-12-20
sifive_u: Set 'clock-frequency' DT property for SiFive UART
Anup Patel
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