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AgeCommit message (Expand)Author
2019-09-17riscv: Add a helper routine for finding firmwareBin Meng
2019-09-17riscv: plic: Remove unused interrupt functionsAlistair Francis
2019-09-17riscv: sifive_u: Fix clock-names property for ethernet nodeGuenter Roeck
2019-09-17riscv: sivive_u: Add dummy serial clock and aliases entry for uartGuenter Roeck
2019-09-17riscv: sifive_u: Add support for loading initrdGuenter Roeck
2019-08-16Include sysemu/sysemu.h a lot lessMarkus Armbruster
2019-08-16Include hw/boards.h a bit lessMarkus Armbruster
2019-08-16Include hw/qdev-properties.h lessMarkus Armbruster
2019-08-16Include hw/hw.h exactly where neededMarkus Armbruster
2019-08-16Include migration/vmstate.h lessMarkus Armbruster
2019-08-16Include hw/irq.h a lot lessMarkus Armbruster
2019-08-16Include sysemu/reset.h a lot lessMarkus Armbruster
2019-07-26riscv/boot: Fixup the RISC-V firmware warningAlistair Francis
2019-07-18hw/riscv: Load OpenSBI as the default firmwareAlistair Francis
2019-07-05hw/riscv: Replace global smp variables with machine smp propertiesLike Xu
2019-06-27hw/riscv: Extend the kernel loading supportAlistair Francis
2019-06-27hw/riscv: Add support for loading a firmwareAlistair Francis
2019-06-27hw/riscv: Split out the boot functionsAlistair Francis
2019-06-27riscv: sifive_u: Update the plic hart config to support multicoreBin Meng
2019-06-27riscv: sifive_u: Do not create hard-coded phandles in DTBin Meng
2019-06-25riscv: virt: Add cpu-topology DT node.Atish Patra
2019-06-23RISC-V: Fix a memory leak when realizing a sifive_ePalmer Dabbelt
2019-06-23riscv: virt: Correct pci "bus-range" encodingBin Meng
2019-06-23sifive_prci: Read and write PRCI registersNathaniel Graff
2019-06-12Include qemu/module.h where needed, drop it from qemu-common.hMarkus Armbruster
2019-05-24riscv: spike: Add a generic spike machineAlistair Francis
2019-05-24riscv: virt: Allow specifying a CPU via commandlineAlistair Francis
2019-05-24target/riscv: Remove unused include of riscv_htif.h for virt board riscvJonathan Behrens
2019-05-24SiFive RISC-V GPIO DeviceFabien Chouteau
2019-04-04riscv: plic: Log guest errorsAlistair Francis
2019-04-04riscv: plic: Fix incorrect irq calculationAlistair Francis
2019-03-28Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
2019-03-19riscv: sifive_u: Correct UART0's IRQ in the device treeBin Meng
2019-03-19riscv: sifive_uart: Generate TX interruptBin Meng
2019-03-19riscv: sifive_u: Allow up to 4 CPUs to be createdAlistair Francis
2019-03-19RISC-V: Allow interrupt controllers to claim interruptsMichael Clark
2019-03-19RISC-V: Replace __builtin_popcount with ctpop8 in PLICMichael Clark
2019-03-18kconfig: add CONFIG_MSI_NONBROKENPaolo Bonzini
2019-03-18riscv: plic: Set msi_nonbroken as trueAlistair Francis
2019-03-11riscv/Kconfig: enable PCI_DEVICESDavid Abdurachmanov
2019-03-07riscv-softmmu.mak: replace CONFIG_* with Kconfig "select" directivesPaolo Bonzini
2019-03-07kconfig: introduce kconfig filesPaolo Bonzini
2019-02-11riscv: Ensure the kernel start address is correctly castAlistair Francis
2019-02-05hw/riscv/Makefile.objs: Create CONFIG_* for riscv boardsYang Zhong
2019-02-05elf: Add optional function ptr to load_elf() to parse ELF notesLiam Merwick
2018-12-20sifive_uart: Implement interrupt pending registerNathaniel Graff
2018-12-20RISC-V: Enable second UART on sifive_e and sifive_uMichael Clark
2018-12-20RISC-V: Fix PLIC pending bitfield readsMichael Clark
2018-12-20RISC-V: Fix CLINT timecmp low 32-bit writesMichael Clark
2018-12-20sifive_u: Set 'clock-frequency' DT property for SiFive UARTAnup Patel