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path: root/hw/riscv/virt.c
AgeCommit message (Expand)Author
2021-06-08hw/riscv: Use macros for BIOS image namesBin Meng
2021-06-08hw/riscv: Support the official PLIC DT bindingsBin Meng
2021-06-08hw/riscv: Support the official CLINT DT bindingsBin Meng
2021-06-08hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helperBin Meng
2021-05-02hw: Do not include qemu/log.h if it is not necessaryThomas Huth
2021-03-22hw/riscv: allow ramfb on virtAsherah Connor
2021-03-22hw/riscv: Add fw_cfg support to virtAsherah Connor
2021-03-10hw/riscv: migrate fdt field to generic MachineStateAlex Bennée
2021-03-04hw/riscv: virt: Map high mmio for PCIeBin Meng
2021-03-04hw/riscv: virt: Limit RAM size in a 32-bit systemBin Meng
2021-03-04hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()Bin Meng
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng
2021-01-16riscv: Pass RISCVHartArrayState by pointerAlistair Francis
2020-12-17hw/riscv: Use the CPU to determine if 32-bitAlistair Francis
2020-12-17hw/riscv: virt: Remove compile time XLEN checksAlistair Francis
2020-12-17hw/riscv: boot: Remove compile time XLEN checksAlistair Francis
2020-12-17riscv: virt: Remove target macro conditionalsAlistair Francis
2020-12-15vl: make qemu_get_machine_opts staticPaolo Bonzini
2020-11-03hw/riscv: virt: Allow passing custom DTBAnup Patel
2020-10-22hw/riscv: Load the kernel after the firmwareAlistair Francis
2020-09-09hw/riscv: Move sifive_test model to hw/miscBin Meng
2020-09-09hw/riscv: Move sifive_plic model to hw/intcBin Meng
2020-09-09hw/riscv: Move sifive_clint model to hw/intcBin Meng
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng
2020-08-25hw/riscv: virt: Allow creating multiple NUMA socketsAnup Patel
2020-08-25hw/riscv: Allow creating multiple instances of PLICAnup Patel
2020-08-25hw/riscv: Allow creating multiple instances of CLINTAnup Patel
2020-08-21hw/riscv: Use pre-built bios image of generic platform for virt & sifive_uBin Meng
2020-07-13hw/riscv: Modify MROM size to end at 0x10000Bin Meng
2020-07-13riscv: Add opensbi firmware dynamic supportAtish Patra
2020-07-13RISC-V: Copy the fdt in dram instead of ROMAtish Patra
2020-07-13riscv: Unify Qemu's reset vector code pathAtish Patra
2020-07-13hw/riscv: virt: Sort the SoC memmap table entriesBin Meng
2020-07-10qom: Put name parameter before value / visitor parameterMarkus Armbruster
2020-06-15sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1Markus Armbruster
2020-06-15sysbus: Convert to sysbus_realize() etc. with CoccinelleMarkus Armbruster
2020-06-15qdev: Convert uses of qdev_create() manuallyMarkus Armbruster
2020-06-15qdev: Convert uses of qdev_create() with CoccinelleMarkus Armbruster
2020-06-15riscv: Fix to put "riscv.hart_array" devices on sysbusMarkus Armbruster
2020-06-03hw/riscv: virt: Remove the riscv_ prefix of the machine* functionsBin Meng
2020-05-18hw: Use QEMU_IS_ALIGNED() on parallel flash block sizePhilippe Mathieu-Daudé
2020-05-15qom: Drop parameter @errp of object_property_add() & friendsMarkus Armbruster
2020-04-29hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()Anup Patel
2020-04-29hw/riscv: Generate correct "mmu-type" for 32-bit machinesBin Meng
2020-02-27hw/riscv: Provide rdtime callback for TCG in CLINT emulationAnup Patel
2020-02-27riscv: virt: Allow PCI address 0Bin Meng
2020-02-10riscv: virt: Use Goldfish RTC deviceAnup Patel
2020-02-10riscv/virt: Add syscon reboot and poweroff DT nodesAnup Patel
2019-11-25hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()Zhuang, Siwei (Data61, Kensington NSW)
2019-11-25RISC-V: virt: This is a "sifive,test1" test finisherPalmer Dabbelt
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