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path: root/hw/riscv/virt.c
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2020-02-27hw/riscv: Provide rdtime callback for TCG in CLINT emulationAnup Patel
This patch extends CLINT emulation to provide rdtime callback for TCG. This rdtime callback will be called wheneven TIME CSRs are read in privileged modes. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-02-27riscv: virt: Allow PCI address 0Bin Meng
When testing e1000 with the virt machine, e1000's I/O space cannot be accessed. Debugging shows that the I/O BAR (BAR1) is correctly written with address 0 plus I/O enable bit, but QEMU's "info pci" shows that: Bus 0, device 1, function 0: Ethernet controller: PCI device 8086:100e ... BAR1: I/O at 0xffffffffffffffff [0x003e]. ... It turns out we should set pci_allow_0_address to true to allow 0 PCI address, otherwise pci_bar_address() treats such address as PCI_BAR_UNMAPPED. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-02-10riscv: virt: Use Goldfish RTC deviceAnup Patel
We extend QEMU RISC-V virt machine by adding Goldfish RTC device to it. This will allow Guest Linux to sync it's local date/time with Host date/time via RTC device. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Acked-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-02-10riscv/virt: Add syscon reboot and poweroff DT nodesAnup Patel
The SiFive test device found on virt machine can be used by generic syscon reboot and poweroff drivers available in Linux kernel. This patch updates FDT generation in virt machine so that Linux kernel can probe and use generic syscon drivers. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2019-11-25hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()Zhuang, Siwei (Data61, Kensington NSW)
This patch adds an optional function pointer, "sym_cb", to riscv_load_kernel() which provides the possibility to access the symbol table during kernel loading. The pointer is ignored, if supplied with Image or uImage file. The Spike board requires the access to locate the HTIF symbols. Fixes: 0ac24d56c5e7 ("hw/riscv: Split out the boot functions") Buglink: https://bugs.launchpad.net/qemu/+bug/1835827 Signed-off-by: Siwei Zhuang <siwei.zhuang@data61.csiro.au> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2019-11-25RISC-V: virt: This is a "sifive,test1" test finisherPalmer Dabbelt
The test finisher implements the reset command, which means it's a "sifive,test1" device. This is a backwards compatible change, so it's also a "sifive,test0" device. I copied the odd idiom for adding a two-string compatible field from the ARM virt board. Fixes: 9a2551ed6f ("riscv: sifive_test: Add reset functionality") Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2019-11-14riscv/virt: Increase flash sizeAlistair Francis
Coreboot developers have requested that they have at least 32MB of flash to load binaries. We currently have 32MB of flash, but it is split in two to allow loading two flash binaries. Let's increase the flash size from 32MB to 64MB to ensure we have a single region that is 32MB. No QEMU release has include flash in the RISC-V virt machine, so this isn't a breaking change. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28riscv/virt: Jump to pflash if specifiedAlistair Francis
If the user supplied pflash to QEMU then change the reset code to jump to the pflash base address instead of the DRAM base address. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28riscv/virt: Add the PFlash CFI01 deviceAlistair Francis
Add the CFI01 PFlash to the RISC-V virt board. This is the same PFlash from the ARM Virt board and the implementation is based on the ARM Virt board. This allows users to specify flash files from the command line. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28riscv/virt: Manually define the machineAlistair Francis
Instead of using the DEFINE_MACHINE() macro to define the machine let's do it manually. This allows us to use the machine object to create RISCVVirtState. This is required to add children and aliases to the machine. This patch is no functional change. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28riscv: hw: Drop "clock-frequency" property of cpu nodesBin Meng
The "clock-frequency" property of cpu nodes isn't required. Drop it. This is to keep in sync with Linux kernel commit below: https://patchwork.kernel.org/patch/11133031/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: hw: Change create_fdt() to return voidBin Meng
There is no need to return fdt at the end of create_fdt() because it's already saved in s->fdt. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: hw: Remove not needed PLIC properties in device treeBin Meng
This removes "reg-names" and "riscv,max-priority" properties of the PLIC node from device tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jonathan Behrens <fintelia@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cellBin Meng
Some of the properties only have 1 cell so we should use qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: hw: Remove superfluous "linux, phandle" propertyBin Meng
"linux,phandle" property is optional. Remove all instances in the sifive_u, virt and spike machine device trees. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-08-16Include sysemu/sysemu.h a lot lessMarkus Armbruster
In my "build everything" tree, changing sysemu/sysemu.h triggers a recompile of some 5400 out of 6600 objects (not counting tests and objects that don't depend on qemu/osdep.h). hw/qdev-core.h includes sysemu/sysemu.h since recent commit e965ffa70a "qdev: add qdev_add_vm_change_state_handler()". This is a bad idea: hw/qdev-core.h is widely included. Move the declaration of qdev_add_vm_change_state_handler() to sysemu/sysemu.h, and drop the problematic include from hw/qdev-core.h. Touching sysemu/sysemu.h now recompiles some 1800 objects. qemu/uuid.h also drops from 5400 to 1800. A few more headers show smaller improvement: qemu/notify.h drops from 5600 to 5200, qemu/timer.h from 5600 to 4500, and qapi/qapi-types-run-state.h from 5500 to 5000. Cc: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20190812052359.30071-28-armbru@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2019-08-16Include hw/hw.h exactly where neededMarkus Armbruster
In my "build everything" tree, changing hw/hw.h triggers a recompile of some 2600 out of 6600 objects (not counting tests and objects that don't depend on qemu/osdep.h). The previous commits have left only the declaration of hw_error() in hw/hw.h. This permits dropping most of its inclusions. Touching it now recompiles less than 200 objects. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20190812052359.30071-19-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-07-18hw/riscv: Load OpenSBI as the default firmwareAlistair Francis
If the user hasn't specified a firmware to load (with -bios) or specified no bios (with -bios none) then load OpenSBI by default. This allows users to boot a RISC-V kernel with just -kernel. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-07-05hw/riscv: Replace global smp variables with machine smp propertiesLike Xu
The global smp variables in riscv are replaced with smp machine properties. A local variable of the same name would be introduced in the declaration phase if it's used widely in the context OR replace it on the spot if it's only used once. No semantic changes. Signed-off-by: Like Xu <like.xu@linux.intel.com> Message-Id: <20190518205428.90532-6-like.xu@linux.intel.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> [ehabkost: fix spike_board_init()] [ehabkost: fix riscv_sifive_e_soc_init()] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-06-27hw/riscv: Add support for loading a firmwareAlistair Francis
Add support for loading a firmware file for the virt machine and the SiFive U. This can be run with the following command: qemu-system-riscv64 -machine virt -bios fw_jump.bin -kernel vmlinux Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-27hw/riscv: Split out the boot functionsAlistair Francis
Split the common RISC-V boot functions into a seperate file. This allows us to share the common code. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-25riscv: virt: Add cpu-topology DT node.Atish Patra
Currently, there is no cpu topology defined in RISC-V. Define a device tree node that clearly describes the entire topology. This saves the trouble of scanning individual cache to figure out the topology. Here is the linux kernel patch series that enables topology for RISC-V. http://lists.infradead.org/pipermail/linux-riscv/2019-June/005072.html CPU topology after applying this patch in QEMU & above series in kernel / # cat /sys/devices/system/cpu/cpu2/topology/thread_siblings_list 2 / # cat /sys/devices/system/cpu/cpu2/topology/physical_package_id 0 / # cat /sys/devices/system/cpu/cpu2/topology/core_siblings_list 0-7 Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-23riscv: virt: Correct pci "bus-range" encodingBin Meng
The largest pci bus number should be calculated from ECAM size, instead of its base address. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24riscv: virt: Allow specifying a CPU via commandlineAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-24target/riscv: Remove unused include of riscv_htif.h for virt board riscvJonathan Behrens
Signed-off-by: Jonathan Behrens <fintelia@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11riscv: Ensure the kernel start address is correctly castAlistair Francis
Cast the kernel start address to the target bit length. This ensures that we calculate the initrd offset to a valid address for the architecture. Steps to reproduce the original problem (reported by Alex): Build U-Boot for the virt machine for riscv32. Then run it with $ qemu-system-riscv32 -M virt -kernel u-boot -nographic -initrd <a file> You can find the initrd address with U-Boot# fdt addr $fdtcontroladdr U-Boot# fdt ls /chosen Then take a peek at that address: U-Boot# md.b <addr> and you will see that there is nothing there without this patch. The reason is that the binary was loaded to a negative address. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Suggested-by: Alexander Graf <agraf@suse.de> Reported-by: Alexander Graf <agraf@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-05elf: Add optional function ptr to load_elf() to parse ELF notesLiam Merwick
This patch adds an optional function pointer, 'elf_note_fn', to load_elf() which causes load_elf() to additionally parse any ELF program headers of type PT_NOTE and check to see if the ELF Note is of the type specified by the 'translate_opaque' arg. If a matching ELF Note is found then the specfied function pointer is called to process the ELF note. Passing a NULL function pointer results in ELF Notes being skipped. The first consumer of this functionality is the PVHboot support which needs to read the XEN_ELFNOTE_PHYS32_ENTRY ELF Note while loading the uncompressed kernel binary in order to discover the boot entry address for the x86/HVM direct boot ABI. Signed-off-by: Liam Merwick <liam.merwick@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-12-20hw/riscv/virt: Connect the gpex PCIeAlistair Francis
Connect the gpex PCIe device based on the device tree included in the HiFive Unleashed ROM. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Andrea Bolognani <abologna@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-12-20hw/riscv/virt: Adjust memory layout spacingAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Andrea Bolognani <abologna@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-11-13hw/riscv/virt: Free the test device tree node nameAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-10-17RISC-V: Don't add NULL bootargs to device-treeMichael Clark
Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-10-17RISC-V: Add missing free for plic_hart_configMichael Clark
Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-09-25Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-09-24' ↵Peter Maydell
into staging Error reporting & miscellaneous patches for 2018-09-24 # gpg: Signature made Mon 24 Sep 2018 16:16:50 BST # gpg: using RSA key 3870B400EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-error-2018-09-24: MAINTAINERS: Fix F: patterns that don't match anything Drop "qemu:" prefix from error_report() arguments qemu-error: make use of {error, warn}_report_once_cond qemu-error: add {error, warn}_report_once_cond Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-24Drop "qemu:" prefix from error_report() argumentsMao Zhongyi
error_report and friends already add a "qemu-system-xxx" prefix to the string, so a "qemu:" prefix is redundant in the string. Just drop it. Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1537495530-580-1-git-send-email-maozhongyi@cmss.chinamobile.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2018-09-05hw/riscv/virtio: Set the soc device tree node as a simple-busAlistair Francis
To allow Linux to enumerate devices on the /soc/ node set it as a "simple-bus". Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-07-19virt: Fix crash when introspecting the deviceAlistair Francis
Use the new object_initialize_child() and sysbus_init_child_obj() to fix the issue. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Suggested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Michael Clark <mjc@sifive.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-07-05hw/riscv/sifive_plic: Use gpios instead of irqsAlistair Francis
Instead of creating the interrupt in lines with qemu_allocate_irq() use qdev_init_gpio_in() as this gives us the ability to use the qdev*gpio*() helpers later on. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Michael Clark <mjc@sifive.com>
2018-07-02hw/riscv: Use the IEC binary prefix definitionsPhilippe Mathieu-Daudé
It eases code review, unit is explicit. Patch generated using: $ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/ and modified manually. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Michael Clark <mjc@sifive.com> Message-Id: <20180625124238.25339-17-f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-05-06RISC-V: Mark ROM read-only after copying in codeMichael Clark
The sifive_u machine already marks its ROM readonly however it has the wrong base address for its mask ROM. This patch fixes the sifive_u mask ROM base address. This commit makes all other boards consistently use mask_rom as the variable name for their ROMs. Boards that use device tree now check that that the device tree fits in the assigned ROM space using the new qemu_fdt_totalsize(void *fdt) interface, adding a bounds check and error message. This can detect truncation. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <Alistair.Francis@wdc.com>
2018-05-06RISC-V: Remove EM_RISCV ELF_MACHINE indirectionMichael Clark
Pointless indirection. Other ports use EM_ constants directly. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Remove unused class definitionsMichael Clark
Removes a whole lot of unnecessary boilerplate code. Machines don't need to be objects. The expansion of the SOC object model for the RISC-V machines will happen in the future as SiFive plans to add their FE310 and FU540 SOCs to QEMU. However, it seems that this present boilerplate is complete unnecessary. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Remove identity_translate from load_elfMichael Clark
When load_elf is called with NULL as an argument to the address translate callback, it does an identity translation. This commit removes the redundant identity_translate callback. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Use ROM base address and size from memmapMichael Clark
Another case of replacing hard coded constants, this time referring to the definition in the virt machine's memmap. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Make virt board description match spikeMichael Clark
This makes 'qemu-system-riscv64 -machine help' output more tidy and consistent. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Replace hardcoded constants with enum valuesMichael Clark
The RISC-V device-tree code has a number of hard-coded constants and this change moves them into header enums. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-04-26Change references to serial_hds[] to serial_hd()Peter Maydell
Change all the uses of serial_hds[] to go via the new serial_hd() function. Code change produced with: find hw -name '*.[ch]' | xargs sed -i -e 's/serial_hds\[\([^]]*\)\]/serial_hd(\1)/g' Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20180420145249.32435-8-peter.maydell@linaro.org
2018-03-07RISC-V VirtIO MachineMichael Clark
RISC-V machine with device-tree, 16550a UART and VirtIO MMIO. The following machine is implemented: - 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-16 04:13:41 +0000