| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-05-24 | SiFive RISC-V GPIO Device | Fabien Chouteau | |
| QEMU model of the GPIO device on the SiFive E300 series SOCs. The pins are not used by a board definition yet, however this implementation can already be used to trigger GPIO interrupts from the software by configuring a pin as both output and input. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> | |||
 |
index : slackcoder/qemu | |
| QEMU is a generic and open source machine & userspace emulator and virtualizer | Mirror |
| aboutsummaryrefslogtreecommitdiff |