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path: root/hw/riscv/sifive_u.c
AgeCommit message (Expand)Author
2019-03-19riscv: sifive_u: Correct UART0's IRQ in the device treeBin Meng
2019-03-19riscv: sifive_u: Allow up to 4 CPUs to be createdAlistair Francis
2019-02-11riscv: Ensure the kernel start address is correctly castAlistair Francis
2019-02-05elf: Add optional function ptr to load_elf() to parse ELF notesLiam Merwick
2018-12-20RISC-V: Enable second UART on sifive_e and sifive_uMichael Clark
2018-12-20sifive_u: Set 'clock-frequency' DT property for SiFive UARTAnup Patel
2018-12-20sifive_u: Add clock DT node for GEM ethernetAnup Patel
2018-10-17RISC-V: Don't add NULL bootargs to device-treeMichael Clark
2018-09-24Drop "qemu:" prefix from error_report() argumentsMao Zhongyi
2018-07-19sifive_u: Fix crash when introspecting the deviceAlistair Francis
2018-07-05hw/riscv/sifive_u: Connect the Cadence GEM Ethernet deviceAlistair Francis
2018-07-05hw/riscv/sifive_u: Move the uart device tree node under /soc/Alistair Francis
2018-07-05hw/riscv/sifive_u: Set the interrupt controller number of interruptsAlistair Francis
2018-07-05hw/riscv/sifive_u: Set the soc device tree node as a simple-busAlistair Francis
2018-07-05hw/riscv/sifive_plic: Use gpios instead of irqsAlistair Francis
2018-07-05hw/riscv/sifive_u: Create a SiFive U SoC objectAlistair Francis
2018-05-06RISC-V: Mark ROM read-only after copying in codeMichael Clark
2018-05-06RISC-V: Remove EM_RISCV ELF_MACHINE indirectionMichael Clark
2018-05-06RISC-V: Remove unused class definitionsMichael Clark
2018-05-06RISC-V: Remove identity_translate from load_elfMichael Clark
2018-05-06RISC-V: Replace hardcoded constants with enum valuesMichael Clark
2018-04-26Change references to serial_hds[] to serial_hd()Peter Maydell
2018-03-07SiFive Freedom U Series RISC-V MachineMichael Clark