Age | Commit message (Expand) | Author |
2019-03-19 | riscv: sifive_u: Correct UART0's IRQ in the device tree | Bin Meng |
2019-03-19 | riscv: sifive_u: Allow up to 4 CPUs to be created | Alistair Francis |
2019-02-11 | riscv: Ensure the kernel start address is correctly cast | Alistair Francis |
2019-02-05 | elf: Add optional function ptr to load_elf() to parse ELF notes | Liam Merwick |
2018-12-20 | RISC-V: Enable second UART on sifive_e and sifive_u | Michael Clark |
2018-12-20 | sifive_u: Set 'clock-frequency' DT property for SiFive UART | Anup Patel |
2018-12-20 | sifive_u: Add clock DT node for GEM ethernet | Anup Patel |
2018-10-17 | RISC-V: Don't add NULL bootargs to device-tree | Michael Clark |
2018-09-24 | Drop "qemu:" prefix from error_report() arguments | Mao Zhongyi |
2018-07-19 | sifive_u: Fix crash when introspecting the device | Alistair Francis |
2018-07-05 | hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device | Alistair Francis |
2018-07-05 | hw/riscv/sifive_u: Move the uart device tree node under /soc/ | Alistair Francis |
2018-07-05 | hw/riscv/sifive_u: Set the interrupt controller number of interrupts | Alistair Francis |
2018-07-05 | hw/riscv/sifive_u: Set the soc device tree node as a simple-bus | Alistair Francis |
2018-07-05 | hw/riscv/sifive_plic: Use gpios instead of irqs | Alistair Francis |
2018-07-05 | hw/riscv/sifive_u: Create a SiFive U SoC object | Alistair Francis |
2018-05-06 | RISC-V: Mark ROM read-only after copying in code | Michael Clark |
2018-05-06 | RISC-V: Remove EM_RISCV ELF_MACHINE indirection | Michael Clark |
2018-05-06 | RISC-V: Remove unused class definitions | Michael Clark |
2018-05-06 | RISC-V: Remove identity_translate from load_elf | Michael Clark |
2018-05-06 | RISC-V: Replace hardcoded constants with enum values | Michael Clark |
2018-04-26 | Change references to serial_hds[] to serial_hd() | Peter Maydell |
2018-03-07 | SiFive Freedom U Series RISC-V Machine | Michael Clark |