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path: root/hw/riscv/sifive_u.c
AgeCommit message (Expand)Author
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng
2021-03-04hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng
2021-03-04hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng
2021-01-16riscv: Pass RISCVHartArrayState by pointerAlistair Francis
2021-01-16hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_typeBin Meng
2020-12-17hw/riscv: Use the CPU to determine if 32-bitAlistair Francis
2020-12-17hw/riscv: sifive_u: Remove compile time XLEN checksAlistair Francis
2020-12-17hw/riscv: boot: Remove compile time XLEN checksAlistair Francis
2020-12-17hw/riscv: sifive_u: Add UART1 DT node in the generated DTBAnup Patel
2020-12-15vl: make qemu_get_machine_opts staticPaolo Bonzini
2020-11-03hw/riscv: sifive_u: Allow passing custom DTBAnup Patel
2020-10-22hw/riscv: Load the kernel after the firmwareAlistair Francis
2020-10-22hw/riscv: sifive_u: Allow specifying the CPUAlistair Francis
2020-09-22sifive_u: Register "start-in-flash" as class propertyEduardo Habkost
2020-09-18sifive_u: Rename memmap enum constantsEduardo Habkost
2020-09-09hw/riscv: Move sifive_uart model to hw/charBin Meng
2020-09-09hw/riscv: Move sifive_plic model to hw/intcBin Meng
2020-09-09hw/riscv: Move sifive_clint model to hw/intcBin Meng
2020-09-09hw/riscv: sifive_u: Connect a DMA controllerBin Meng
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng
2020-09-09target/riscv: cpu: Set reset vector based on the configured property valueBin Meng
2020-08-25hw/riscv: Allow creating multiple instances of PLICAnup Patel
2020-08-25hw/riscv: Allow creating multiple instances of CLINTAnup Patel
2020-08-21hw/riscv: Use pre-built bios image of generic platform for virt & sifive_uBin Meng
2020-08-21hw/riscv: sifive_u: Add a dummy L2 cache controller deviceBin Meng
2020-07-21hw: Mark nd_table[] misuse in realize methods FIXMEMarkus Armbruster
2020-07-13hw/riscv: Modify MROM size to end at 0x10000Bin Meng
2020-07-13RISC-V: Support 64 bit start addressAtish Patra
2020-07-13riscv: Add opensbi firmware dynamic supportAtish Patra
2020-07-13RISC-V: Copy the fdt in dram instead of ROMAtish Patra
2020-07-13riscv: Unify Qemu's reset vector code pathAtish Patra
2020-07-10error: Eliminate error_propagate() with Coccinelle, part 1Markus Armbruster
2020-07-10qom: Put name parameter before value / visitor parameterMarkus Armbruster
2020-07-10qdev: Use returned bool to check for qdev_realize() etc. failureMarkus Armbruster
2020-07-02riscv/sifive_u: Fix sifive_u_soc_realize() error API violationsMarkus Armbruster
2020-06-19hw/riscv: sifive_u: Add a dummy DDR memory controller deviceBin Meng
2020-06-19hw/riscv: sifive_u: Sort the SoC memmap table entriesBin Meng
2020-06-19hw/riscv: sifive_u: Support different boot source per MSEL pin stateBin Meng
2020-06-19hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng
2020-06-19hw/riscv: sifive_u: Add a new property msel for MSEL pin stateBin Meng
2020-06-19hw/riscv: sifive_u: Rename serial property get/set functions to a generic nameBin Meng
2020-06-19hw/riscv: sifive_u: Add reset functionalityBin Meng
2020-06-19hw/riscv: sifive_u: Hook a GPIO controllerBin Meng
2020-06-19hw/riscv: sifive_u: Generate device tree node for OTPBin Meng
2020-06-19hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bitBin Meng
2020-06-15qdev: Convert bus-less devices to qdev_realize() with CoccinelleMarkus Armbruster
2020-06-15sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2Markus Armbruster
2020-06-15qom: Less verbose object_initialize_child()Markus Armbruster
2020-06-15riscv: Fix to put "riscv.hart_array" devices on sysbusMarkus Armbruster
2020-06-03hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functionsBin Meng
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