Age | Commit message (Collapse) | Author | |
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2018-03-07 | SiFive RISC-V PRCI Block | Michael Clark | |
Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate register reads made by the SDK BSP. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com> |