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path: root/hw/riscv/sifive_e.c
AgeCommit message (Expand)Author
2020-07-10qdev: Use returned bool to check for qdev_realize() etc. failureMarkus Armbruster
2020-06-19hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng
2020-06-19hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng
2020-06-19sifive_e: Support the revB machineAlistair Francis
2020-06-15qdev: Convert bus-less devices to qdev_realize() with CoccinelleMarkus Armbruster
2020-06-15sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2Markus Armbruster
2020-06-15qom: Less verbose object_initialize_child()Markus Armbruster
2020-06-15riscv: Fix to put "riscv.hart_array" devices on sysbusMarkus Armbruster
2020-06-03riscv: sifive_e: Manually define the machineAlistair Francis
2020-04-29riscv: sifive_e: Support changing CPU typeCorey Wharton
2020-03-17hw/riscv: Let devices own the MemoryRegion they createPhilippe Mathieu-Daudé
2020-03-17hw/riscv: Use memory_region_init_rom() with read-only regionsPhilippe Mathieu-Daudé
2020-02-27hw/riscv: Provide rdtime callback for TCG in CLINT emulationAnup Patel
2019-11-25hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()Zhuang, Siwei (Data61, Kensington NSW)
2019-09-17riscv: sifive_e: Drop sifive_mmio_emulate()Bin Meng
2019-09-17riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}Bin Meng
2019-08-16Include sysemu/sysemu.h a lot lessMarkus Armbruster
2019-08-16Include hw/hw.h exactly where neededMarkus Armbruster
2019-07-05hw/riscv: Replace global smp variables with machine smp propertiesLike Xu
2019-06-27hw/riscv: Split out the boot functionsAlistair Francis
2019-06-23RISC-V: Fix a memory leak when realizing a sifive_ePalmer Dabbelt
2019-05-24SiFive RISC-V GPIO DeviceFabien Chouteau
2019-02-11riscv: Ensure the kernel start address is correctly castAlistair Francis
2019-02-05elf: Add optional function ptr to load_elf() to parse ELF notesLiam Merwick
2018-12-20RISC-V: Enable second UART on sifive_e and sifive_uMichael Clark
2018-09-24Drop "qemu:" prefix from error_report() argumentsMao Zhongyi
2018-07-19sifive_e: Fix crash when introspecting the deviceAlistair Francis
2018-07-05hw/riscv/sifive_plic: Use gpios instead of irqsAlistair Francis
2018-07-05hw/riscv/sifive_e: Create a SiFive E SoC objectAlistair Francis
2018-05-06RISC-V: Mark ROM read-only after copying in codeMichael Clark
2018-05-06RISC-V: Remove EM_RISCV ELF_MACHINE indirectionMichael Clark
2018-05-06RISC-V: Remove unused class definitionsMichael Clark
2018-05-06RISC-V: Remove identity_translate from load_elfMichael Clark
2018-04-26Change references to serial_hds[] to serial_hd()Peter Maydell
2018-03-07SiFive Freedom E Series RISC-V MachineMichael Clark