slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2022-05-24	hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)	Tsukasa OI
2022-01-08	hw/riscv: Use error_fatal for SoC realisation	Alistair Francis
2021-10-22	hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id	Bin Meng
2021-09-21	hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT	Anup Patel
2021-09-21	hw/intc: Rename sifive_clint sources to riscv_aclint sources	Anup Patel
2021-09-21	hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines	Alistair Francis
2021-08-26	arch_init.h: Don't include arch_init.h unnecessarily	Peter Maydell
2021-05-11	hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]	Bin Meng
2021-05-02	Do not include exec/address-spaces.h if it's not really necessary	Thomas Huth
2021-05-02	hw: Do not include qemu/log.h if it is not necessary	Thomas Huth
2021-03-04	hw/riscv: Drop 'struct MemmapEntry'	Bin Meng
2020-10-22	hw/riscv: Load the kernel after the firmware	Alistair Francis
2020-09-22	sifive_e: Register "revb" as class property	Eduardo Habkost
2020-09-18	sifive_e: Rename memmap enum constants	Eduardo Habkost
2020-09-09	hw/riscv: Move sifive_uart model to hw/char	Bin Meng
2020-09-09	hw/riscv: Move sifive_plic model to hw/intc	Bin Meng
2020-09-09	hw/riscv: Move sifive_clint model to hw/intc	Bin Meng
2020-09-09	hw/riscv: Move sifive_e_prci model to hw/misc	Bin Meng
2020-09-09	hw/riscv: clint: Avoid using hard-coded timebase frequency	Bin Meng
2020-09-09	target/riscv: cpu: Set reset vector based on the configured property value	Bin Meng
2020-08-25	hw/riscv: Allow creating multiple instances of PLIC	Anup Patel
2020-08-25	hw/riscv: Allow creating multiple instances of CLINT	Anup Patel
2020-07-22	hw/riscv: sifive_e: Correct debug block size	Bin Meng
2020-07-10	error: Eliminate error_propagate() with Coccinelle, part 1	Markus Armbruster
2020-07-10	qom: Put name parameter before value / visitor parameter	Markus Armbruster
2020-07-10	qdev: Use returned bool to check for qdev_realize() etc. failure	Markus Armbruster
2020-06-19	hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004	Bin Meng
2020-06-19	hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions	Bin Meng
2020-06-19	sifive_e: Support the revB machine	Alistair Francis
2020-06-15	qdev: Convert bus-less devices to qdev_realize() with Coccinelle	Markus Armbruster
2020-06-15	sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2	Markus Armbruster
2020-06-15	qom: Less verbose object_initialize_child()	Markus Armbruster
2020-06-15	riscv: Fix to put "riscv.hart_array" devices on sysbus	Markus Armbruster
2020-06-03	riscv: sifive_e: Manually define the machine	Alistair Francis
2020-04-29	riscv: sifive_e: Support changing CPU type	Corey Wharton
2020-03-17	hw/riscv: Let devices own the MemoryRegion they create	Philippe Mathieu-Daudé
2020-03-17	hw/riscv: Use memory_region_init_rom() with read-only regions	Philippe Mathieu-Daudé
2020-02-27	hw/riscv: Provide rdtime callback for TCG in CLINT emulation	Anup Patel
2019-11-25	hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()	Zhuang, Siwei (Data61, Kensington NSW)
2019-09-17	riscv: sifive_e: Drop sifive_mmio_emulate()	Bin Meng
2019-09-17	riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}	Bin Meng
2019-08-16	Include sysemu/sysemu.h a lot less	Markus Armbruster
2019-08-16	Include hw/hw.h exactly where needed	Markus Armbruster
2019-07-05	hw/riscv: Replace global smp variables with machine smp properties	Like Xu
2019-06-27	hw/riscv: Split out the boot functions	Alistair Francis
2019-06-23	RISC-V: Fix a memory leak when realizing a sifive_e	Palmer Dabbelt
2019-05-24	SiFive RISC-V GPIO Device	Fabien Chouteau
2019-02-11	riscv: Ensure the kernel start address is correctly cast	Alistair Francis
2019-02-05	elf: Add optional function ptr to load_elf() to parse ELF notes	Liam Merwick
2018-12-20	RISC-V: Enable second UART on sifive_e and sifive_u	Michael Clark