slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2022-04-22	riscv: opentitan: Connect opentitan SPI Host	Wilfred Mallawa
2022-03-03	hw: riscv: opentitan: fixup SPI addresses	Wilfred Mallawa
2022-01-21	riscv: opentitan: fixup plic stride len	Wilfred Mallawa
2022-01-08	hw/riscv: Use error_fatal for SoC realisation	Alistair Francis
2021-10-28	hw/riscv: opentitan: Fixup the PLIC context addresses	Alistair Francis
2021-10-22	hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id	Bin Meng
2021-10-22	hw/riscv: opentitan: Update to the latest build	Alistair Francis
2021-09-21	hw/riscv: opentitan: Correct the USB Dev address	Alistair Francis
2021-09-21	hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines	Alistair Francis
2021-09-21	hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines	Alistair Francis
2021-07-15	hw/riscv: opentitan: Add the flash alias	Alistair Francis
2021-07-15	hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri	Alistair Francis
2021-06-24	hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer	Alistair Francis
2021-05-11	hw/riscv: Fix OT IBEX reset vector	Alexander Wagner
2021-05-11	hw/opentitan: Update the interrupt layout	Alistair Francis
2021-05-02	Do not include exec/address-spaces.h if it's not really necessary	Thomas Huth
2021-03-04	hw/riscv: Drop 'struct MemmapEntry'	Bin Meng
2020-12-17	riscv/opentitan: Update the OpenTitan memory layout	Alistair Francis
2020-10-22	hw/riscv: Load the kernel after the firmware	Alistair Francis
2020-09-09	target/riscv: cpu: Set reset vector based on the configured property value	Bin Meng
2020-08-27	opentitan: Rename memmap enum constants	Eduardo Habkost
2020-07-10	error: Eliminate error_propagate() with Coccinelle, part 1	Markus Armbruster
2020-07-10	qom: Put name parameter before value / visitor parameter	Markus Armbruster
2020-07-10	qdev: Use returned bool to check for qdev_realize() etc. failure	Markus Armbruster
2020-06-19	hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions	Bin Meng
2020-06-19	riscv/opentitan: Connect the UART device	Alistair Francis
2020-06-19	riscv/opentitan: Connect the PLIC device	Alistair Francis
2020-06-19	riscv/opentitan: Fix the ROM size	Alistair Francis
2020-06-15	qdev: Convert bus-less devices to qdev_realize() with Coccinelle	Markus Armbruster
2020-06-15	sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2	Markus Armbruster
2020-06-15	qom: Less verbose object_initialize_child()	Markus Armbruster
2020-06-15	riscv: Fix to put "riscv.hart_array" devices on sysbus	Markus Armbruster
2020-06-03	riscv: Initial commit of OpenTitan machine	Alistair Francis