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path: root/hw/riscv/opentitan.c
AgeCommit message (Expand)Author
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng
2020-12-17riscv/opentitan: Update the OpenTitan memory layoutAlistair Francis
2020-10-22hw/riscv: Load the kernel after the firmwareAlistair Francis
2020-09-09target/riscv: cpu: Set reset vector based on the configured property valueBin Meng
2020-08-27opentitan: Rename memmap enum constantsEduardo Habkost
2020-07-10error: Eliminate error_propagate() with Coccinelle, part 1Markus Armbruster
2020-07-10qom: Put name parameter before value / visitor parameterMarkus Armbruster
2020-07-10qdev: Use returned bool to check for qdev_realize() etc. failureMarkus Armbruster
2020-06-19hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng
2020-06-19riscv/opentitan: Connect the UART deviceAlistair Francis
2020-06-19riscv/opentitan: Connect the PLIC deviceAlistair Francis
2020-06-19riscv/opentitan: Fix the ROM sizeAlistair Francis
2020-06-15qdev: Convert bus-less devices to qdev_realize() with CoccinelleMarkus Armbruster
2020-06-15sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2Markus Armbruster
2020-06-15qom: Less verbose object_initialize_child()Markus Armbruster
2020-06-15riscv: Fix to put "riscv.hart_array" devices on sysbusMarkus Armbruster
2020-06-03riscv: Initial commit of OpenTitan machineAlistair Francis