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path: root/hw/riscv/microchip_pfsoc.c
AgeCommit message (Expand)Author
2020-11-03hw/riscv: microchip_pfsoc: Hook the I2C1 controllerBin Meng
2020-11-03hw/riscv: microchip_pfsoc: Correct DDR memory mapBin Meng
2020-11-03hw/riscv: microchip_pfsoc: Map the reserved memory at address 0Bin Meng
2020-11-03hw/riscv: microchip_pfsoc: Connect the SYSREG moduleBin Meng
2020-11-03hw/riscv: microchip_pfsoc: Connect the IOSCB moduleBin Meng
2020-11-03hw/riscv: microchip_pfsoc: Connect DDR memory controller modulesBin Meng
2020-11-03hw/riscv: microchip_pfsoc: Document where to look at the SoC memory mapsBin Meng
2020-09-09hw/riscv: Move sifive_plic model to hw/intcBin Meng
2020-09-09hw/riscv: Move sifive_clint model to hw/intcBin Meng
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng
2020-09-09hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng
2020-09-09hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng
2020-09-09hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng
2020-09-09hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng
2020-09-09hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng
2020-09-09hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng
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