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path: root/hw/riscv/meson.build
AgeCommit message (Expand)Author
2020-09-09hw/riscv: Always build riscv_hart.cBin Meng
2020-09-09hw/riscv: Move sifive_test model to hw/miscBin Meng
2020-09-09hw/riscv: Move sifive_uart model to hw/charBin Meng
2020-09-09hw/riscv: Move riscv_htif model to hw/charBin Meng
2020-09-09hw/riscv: Move sifive_plic model to hw/intcBin Meng
2020-09-09hw/riscv: Move sifive_clint model to hw/intcBin Meng
2020-09-09hw/riscv: Move sifive_gpio model to hw/gpioBin Meng
2020-09-09hw/riscv: Move sifive_u_otp model to hw/miscBin Meng
2020-09-09hw/riscv: Move sifive_u_prci model to hw/miscBin Meng
2020-09-09hw/riscv: Move sifive_e_prci model to hw/miscBin Meng
2020-09-09hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng
2020-09-08configure: do not include dependency flags in QEMU_CFLAGS and LIBSPaolo Bonzini
2020-08-25hw/riscv: Add helpers for RISC-V multi-socket NUMA machinesAnup Patel
2020-08-21meson: convert hw/arch*Marc-André Lureau