Age | Commit message (Expand) | Author |
2023-01-06 | hw/riscv: Sort machines Kconfig options in alphabetical order | Bin Meng |
2023-01-06 | hw/riscv: Fix opentitan dependency to SIFIVE_PLIC | Bin Meng |
2023-01-06 | hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC | Bin Meng |
2022-04-29 | hw/riscv: Enable TPM backends | Alistair Francis |
2022-04-29 | hw/riscv: virt: Create a platform bus | Alistair Francis |
2022-03-03 | hw/riscv: virt: Add optional AIA IMSIC support to virt machine | Anup Patel |
2022-03-03 | hw/riscv: virt: Add optional AIA APLIC support to virt machine | Anup Patel |
2021-09-21 | hw/intc: Rename sifive_clint sources to riscv_aclint sources | Anup Patel |
2021-09-21 | sifive_u: Connect the SiFive PWM device | Alistair Francis |
2021-09-01 | hw/char: Add config for shakti uart | Vijai Kumar K |
2021-07-20 | hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines | Philippe Mathieu-Daudé |
2021-05-11 | hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine | Alistair Francis |
2021-05-11 | riscv: Add initial support for Shakti C machine | Vijai Kumar K |
2021-03-22 | hw/riscv: Add fw_cfg support to virt | Asherah Connor |
2021-03-04 | hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card | Bin Meng |
2021-03-04 | hw/riscv: sifive_u: Add QSPI0 controller and connect a flash | Bin Meng |
2020-11-03 | hw/riscv: microchip_pfsoc: Connect the SYSREG module | Bin Meng |
2020-11-03 | hw/riscv: microchip_pfsoc: Connect the IOSCB module | Bin Meng |
2020-11-03 | hw/riscv: microchip_pfsoc: Connect DDR memory controller modules | Bin Meng |
2020-09-09 | hw/riscv: Sort the Kconfig options in alphabetical order | Bin Meng |
2020-09-09 | hw/riscv: Drop CONFIG_SIFIVE | Bin Meng |
2020-09-09 | hw/riscv: Always build riscv_hart.c | Bin Meng |
2020-09-09 | hw/riscv: Move sifive_test model to hw/misc | Bin Meng |
2020-09-09 | hw/riscv: Move sifive_uart model to hw/char | Bin Meng |
2020-09-09 | hw/riscv: Move riscv_htif model to hw/char | Bin Meng |
2020-09-09 | hw/riscv: Move sifive_plic model to hw/intc | Bin Meng |
2020-09-09 | hw/riscv: Move sifive_clint model to hw/intc | Bin Meng |
2020-09-09 | hw/riscv: Move sifive_gpio model to hw/gpio | Bin Meng |
2020-09-09 | hw/riscv: Move sifive_u_otp model to hw/misc | Bin Meng |
2020-09-09 | hw/riscv: Move sifive_u_prci model to hw/misc | Bin Meng |
2020-09-09 | hw/riscv: Move sifive_e_prci model to hw/misc | Bin Meng |
2020-09-09 | hw/riscv: sifive_u: Connect a DMA controller | Bin Meng |
2020-09-09 | hw/riscv: microchip_pfsoc: Connect a DMA controller | Bin Meng |
2020-09-09 | hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card | Bin Meng |
2020-09-09 | hw/riscv: microchip_pfsoc: Connect 5 MMUARTs | Bin Meng |
2020-09-09 | hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board | Bin Meng |
2020-06-19 | hw/char: Initial commit of Ibex UART | Alistair Francis |
2020-06-03 | riscv: Initial commit of OpenTitan machine | Alistair Francis |
2020-02-10 | riscv: virt: Use Goldfish RTC device | Anup Patel |
2019-10-28 | riscv/virt: Add the PFlash CFI01 device | Alistair Francis |
2019-09-17 | riscv: sifive_u: Fix broken GEM support | Bin Meng |
2019-09-17 | riscv: sifive_e: Drop sifive_mmio_emulate() | Bin Meng |
2019-03-18 | kconfig: add CONFIG_MSI_NONBROKEN | Paolo Bonzini |
2019-03-11 | riscv/Kconfig: enable PCI_DEVICES | David Abdurachmanov |
2019-03-07 | riscv-softmmu.mak: replace CONFIG_* with Kconfig "select" directives | Paolo Bonzini |
2019-03-07 | kconfig: introduce kconfig files | Paolo Bonzini |