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2017-09-27Merge remote-tracking branch ↵Peter Maydell
'remotes/dgilbert/tags/pull-migration-20170927a' into staging Migration pull 2017-09-27 # gpg: Signature made Wed 27 Sep 2017 14:56:23 BST # gpg: using RSA key 0x0516331EBC5BFDE7 # gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 45F5 C71B 4A0C B7FB 977A 9FA9 0516 331E BC5B FDE7 * remotes/dgilbert/tags/pull-migration-20170927a: migration: Route more error paths migration: Route errors up through vmstate_save migration: wire vmstate_save_state errors up to vmstate_subsection_save migration: Check field save returns migration: check pre_save return in vmstate_save_state migration: pre_save return int migration: disable auto-converge during bulk block migration Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-27migration: pre_save return intDr. David Alan Gilbert
Modify the pre_save method on VMStateDescription to return an int rather than void so that it potentially can fail. Changed zillions of devices to make them return 0; the only case I've made it return non-0 is hw/intc/s390_flic_kvm.c that already had an error_report/return case. Note: If you add an error exit in your pre_save you must emit an error_report to say why. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20170925112917.21340-2-dgilbert@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2017-09-27macio: use object link between MACIO_IDE and MAC_DBDMA objectMark Cave-Ayland
Using a standard QOM object link we can pass a reference to the MAC_DBDMA controller to the MACIO_IDE object which removes the last external parameter to macio_ide_register_dma(). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-27macio: pass channel into MACIOIDEState via qdev propertyMark Cave-Ayland
One of the reasons macio_ide_register_dma() needs to exist is because the channel id isn't passed into the MACIO_IDE object. Pass in the channel id using a qdev property to remove this requirement. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-27spapr: fix the value of SDR1 in kvmppc_put_books_sregs()Greg Kurz
When running with KVM PR, if a new HPT is allocated we need to inform KVM about the HPT address and size. This is currently done by hacking the value of SDR1 and pushing it to KVM in several places. Also, migration breaks the guest since it is very unlikely the HPT has the same address in source and destination, but we push the incoming value of SDR1 to KVM anyway. This patch introduces a new virtual hypervisor hook so that the spapr code can provide the correct value of SDR1 to be pushed to KVM each time kvmppc_put_books_sregs() is called. It allows to get rid of all the hacking in the spapr/kvmppc code and it fixes migration of nested KVM PR. Suggested-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-27ppc/pnv: check for OPAL firmware file presenceCédric Le Goater
and exit before uselessly trying to load it if the file does not exists. Issue discovered by Coverity Scan. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-27spapr_pci: make index property mandatoryGreg Kurz
PHBs can be created with an index property, in which case the machine code automatically sets all the MMIO windows at addresses derived from the index. Alternatively, they can be manually created without index, but the user has to provide addresses for all MMIO windows. The non-index way happens to be more trouble than it's worth: it's difficult to use, keeps requiring (potentially incompatible) changes when some new parameter needs adding, and is awkward to check for collisions. It currently even has a bug that prevents to use two non-index PHBs because their child DRCs are all derived from the same index == -1 value, and, thus, collide. This patch hence makes the index property mandatory. As a consequence, the PHB's memory regions and BUID are now always configured according to the index, and it is no longer possible to set them from the command line. This DOES BREAK backwards compat, but we don't think the non-index PHB feature was used in practice (at least libvirt doesn't) and the simplification is worth it. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-27spapr: introduce helpers to migrate HPT chunks and the end markerGreg Kurz
This consolidates some duplicated code in a dedicated helpers. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-27ppc/kvm: generalize the use of kvmppc_get_htab_fd()Greg Kurz
The use of KVM_PPC_GET_HTAB_FD is open-coded in kvmppc_read_hptes() and kvmppc_write_hpte(). This patch modifies kvmppc_get_htab_fd() so that it can be used everywhere we need to access the in-kernel htab: - add an index argument => only kvmppc_read_hptes() passes an actual index, all other users pass 0 - add an errp argument to propagate error messages to the caller. => spapr migration code prints the error => hpte helpers pass &error_abort to keep the current behavior of hw_error() While here, this also fixes a bug in kvmppc_write_hpte() so that it opens the htab fd for writing instead of reading as it currently does. This never broke anything because we currently never call this code, as explained in the changelog of commit c1385933804bb: "This support updating htab managed by the hypervisor. Currently we don't have any user for this feature. This actually bring the store_hpte interface in-line with the load_hpte one. We may want to use this when we want to emulate henter hcall in qemu for HV kvm." The above is still true today. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-27ppc/kvm: change kvmppc_get_htab_fd() to return -errno on errorGreg Kurz
When kvmppc_get_htab_fd() fails, its return value is propagated up to qemu_savevm_state_iterate() or to qemu_savevm_state_complete_precopy(). All savevm handlers expect to receive a negative errno on error. Let's patch kvmppc_get_htab_fd() accordingly. While here, let's change htab_load() in the spapr code to also propagate the error, since it doesn't make sense to abort() if we couldn't get the htab fd from KVM. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-27ppc: Fix OpenPIC modelBenjamin Herrenschmidt
Apple uses an IBM MPIC2A without timers, it has 64 sources. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-27ppc/ide/macio: Add missing registersBenjamin Herrenschmidt
The timing register exists on all variants of MacIO IDE, we just store and return its value. The interrupts register only exists on KeyLargo but it doesn't hurt to have it. The lack of this register causes MacOS X to hangs under some circumstances. Both are 32-bit only. The HW might support smaller access sizes but no known OS uses them. Because the core IDE subsystem doesn't provide us with a way to query the main (level) interrupt state, nor do we have a way to know that DBDMA issued a (edge) interrupt, we reflect both through a private pair of qirq's in order to maintain the register state. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-27ppc/mac: Advertise a high clock frequency for NewWorld MacsBenjamin Herrenschmidt
We use 900Mhz, otherwise MacOS X 10.5 refuses to install. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-27ppc: QOMify g3beige machineMark Cave-Ayland
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-27ppc4xx: Add more PLB registersBALATON Zoltan
These registers are present in 440 SoCs (and maybe in others too) and U-Boot accesses them when printing register info. We don't emulate these but add them to avoid crashing when they are read or written. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-26Replace round_page() with TARGET_PAGE_ALIGN()Kamil Rytarowski
This change fixes conflict with the DragonFly BSD headers. Signed-off-by: Kamil Rytarowski <n54@gmx.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-09-19numa: cpu: calculate/set default node-ids after all -numa CLI options are parsedIgor Mammedov
Calculating default node-ids for CPUs in possible_cpu_arch_ids() is rather fragile since defaults calculation uses nb_numa_nodes but callback might be potentially called early before all -numa CLI options are parsed, which would lead to cpus assigned only upto nb_numa_nodes at the time possible_cpu_arch_ids() is called. Issue was introduced by (7c88e65 numa: mirror cpu to node mapping in MachineState::possible_cpus) and for example CLI: -smp 4 -numa node,cpus=0 -numa node would set props.node-id in possible_cpus array for every non explicitly mapped CPU to the first node. Issue is not visible to guest nor to mgmt interface due to 1) implictly mapped cpus are forced to the first node in case of partial mapping 2) in case of default mapping possible_cpu_arch_ids() is called after all -numa options are parsed (resulting in correct mapping). However it's fragile to rely on late execution of possible_cpu_arch_ids(), therefore add machine specific callback that returns node-id for CPU and use it to calculate/ set defaults at machine_numa_finish_init() time when all -numa options are parsed. Reported-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <1496314408-163972-1-git-send-email-imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-09-19cpu: make cpu_generic_init() abort QEMU on errorIgor Mammedov
Almost every user of cpu_generic_init() checks for returned NULL and then reports failure in a custom way and aborts process. Some users assume that call can't fail and don't check for failure, though they should have checked for it. In either cases cpu_generic_init() failure is fatal, so instead of checking for failure and reporting it various ways, make cpu_generic_init() report errors in consistent way and terminate QEMU on failure. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1505318697-77161-3-git-send-email-imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-09-15spapr_events: use QTAILQ_FOREACH_SAFE() in spapr_clear_pending_events()Greg Kurz
QTAILQ_FOREACH_SAFE() must be used when removing the current element inside the loop block. This fixes a user-after-free error introduced by commit 56258174238eb and reported by Coverity (CID 1381017). Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-15spapr_cpu_core: cleaning up qdev_get_machine() callsGreg Kurz
This patch removes the qdev_get_machine() calls that are made in spapr_cpu_core.c in situations where we can get an existing pointer for the MachineState by either passing it as an argument to the function or by using other already available pointers. Credits to Daniel Henrique Barboza for the idea and the changelog text. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-15spapr_pci: don't create 64-bit MMIO window if we don't need toGreg Kurz
When running a pseries-2.2 or older machine type, we get the following lines in info mtree: address-space: memory ... ffffffffffffffff-ffffffffffffffff (prio 0, i/o): alias pci@800000020000000.mmio64-alias @pci@800000020000000.mmio ffffffffffffffff-ffffffffffffffff address-space: cpu-memory ... ffffffffffffffff-ffffffffffffffff (prio 0, i/o): alias pci@800000020000000.mmio64-alias @pci@800000020000000.mmio ffffffffffffffff-ffffffffffffffff The same thing occurs when running a pseries-2.7 with -global spapr-pci-host-bridge.mem_win_size=2147483648 This happens because we always create a 64-bit MMIO window, even if we didn't explicitely requested it (ie, mem64_win_size == 0) and the 32-bit window is below 2GiB. It doesn't seem to have an impact on the guest though because spapr_populate_pci_dt() doesn't advertise the bogus windows when mem64_win_size == 0. Since these memory regions don't induce any state, we can safely choose to not create them when their address is equal to -1, without breaking migration from existing setups. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-15spapr_pci: convert sprintf() to g_strdup_printf()Greg Kurz
In order to follow a QEMU common practice. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-15spapr_cpu_core: fail gracefully with non-pseries machine typesGreg Kurz
Since commit 7cca3e466eb0 ("ppc: spapr: Move VCPU ID calculation into sPAPR"), QEMU aborts when started with a *-spapr-cpu-core device and a non-pseries machine. Let's rely on the already existing call to object_dynamic_cast() instead of using the SPAPR_MACHINE() macro. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-15spapr_pci: handle FDT creation errors with _FDT()Greg Kurz
libfdt failures when creating the FDT should cause QEMU to terminate. Let's use the _FDT() macro which does just that instead of propagating the error to the caller. spapr_populate_pci_child_dt() no longer needs to return a value in this case. Note that, on the way, this get rids of the following nonsensical lines: g_assert(!ret); if (ret) { Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-15spapr_pci: use the common _FDT() helperGreg Kurz
All other users in hw/ppc already consider an error when building the FDT to be fatal, even on hotplug paths. There's no valid reason for spapr_pci to behave differently. So let's used the common _FDT() helper which terminates QEMU when libfdt fails. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-15spapr: fix CAS-generated resetCédric Le Goater
The OV5_MMU_RADIX_300 requires special handling in the CAS negotiation process. It is cleared from the option vector of the guest before evaluating the changes and re-added later. But, when testing for a possible CAS reset : spapr->cas_reboot = spapr_ovec_diff(ov5_updates, ov5_cas_old, spapr->ov5_cas); the bit OV5_MMU_RADIX_300 will each time be seen as removed from the previous OV5 set, hence generating a reset loop. Fix this problem by also clearing the same bit in the ov5_cas_old set. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-15ppc/xive: fix OV5_XIVE_EXPLOIT bitsCédric Le Goater
On POWER9, the Client Architecture Support (CAS) negotiation process determines whether the guest operates in XIVE Legacy compatibility or in XIVE exploitation mode. Now that we have initial guest support for the XIVE interrupt controller, let's fix the bits definition which have evolved in the latest specs. The platform advertises the XIVE Exploitation Mode support using the property "ibm,arch-vec-5-platform-support-vec-5", byte 23 bits 0-1 : - 0b00 XIVE legacy mode Only - 0b01 XIVE exploitation mode Only - 0b10 XIVE legacy or exploitation mode The OS asks for XIVE Exploitation Mode support using the property "ibm,architecture-vec-5", byte 23 bits 0-1: - 0b00 XIVE legacy mode Only - 0b01 XIVE exploitation mode Only Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-15spapr: only update SDR1 once per-cpu during CASGreg Kurz
Commit b55d295e3ec9 added the possibility to support HPT resizing with KVM. In the case of PR, we need to pass the userspace address of the HPT to KVM using the SDR1 slot. This is handled by kvmppc_update_sdr1() which uses CPU_FOREACH() to update all CPUs. It is hence not needed to call kvmppc_update_sdr1() for each CPU. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-15spapr_pci: use g_strdup_printf()Greg Kurz
Building strings with g_strdup_printf() instead of snprintf() is a QEMU common practice. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-15spapr_pci: drop useless check in spapr_populate_pci_child_dt()Greg Kurz
spapr_phb_get_loc_code() either returns a non-null pointer, or aborts if g_strdup_printf() failed to allocate memory. Signed-off-by: Greg Kurz <groug@kaod.org> [dwg: Grammatical fix to commit message] Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-15spapr_pci: drop useless check in spapr_phb_vfio_get_loc_code()Greg Kurz
g_strdup_printf() either returns a non-null pointer, or aborts if it failed to allocate memory. Signed-off-by: Greg Kurz <groug@kaod.org> [dwg: Grammatical fix to commit message] Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-15hw/ppc/spapr.c: cleaning up qdev_get_machine() callsDaniel Henrique Barboza
This patch removes the qdev_get_machine() calls that are made in spapr.c in situations where we can get an existing pointer for the MachineState by either passing it as an argument to the function or by using other already available pointers. The following changes were made: - spapr_node0_size: static function that is called two times: at spapr_setup_hpt_and_vrma and ppc_spapr_init. In both cases we can pass an existing MachineState pointer to it. - spapr_build_fdt: MachineState pointer can be retrieved from the existing sPAPRMachineState pointer. - spapr_boot_set: the opaque in the first arg is a sPAPRMachineState pointer as we can see inside ppc_spapr_init: qemu_register_boot_set(spapr_boot_set, spapr); We can get a MachineState pointer from it. - spapr_machine_device_plug and spapr_machine_device_unplug_request: the MachineState, sPAPRMachineState, MachineClass and sPAPRMachineClass pointers can all be retrieved from the HotplugHandler pointer. Signed-off-by: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc: spapr: Move VCPU ID calculation into sPAPRSam Bobroff
Move the calculation of a CPU's VCPU ID out of the generic PPC code (ppc_cpu_realizefn()) and into sPAPR specific code (spapr_cpu_core_realize()) where it belongs. Unfortunately, due to the way things are ordered, we still need to default the VCPU ID in ppc_cpu_realizfn() but at least doing that doesn't require any interaction with sPAPR. Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc: make cpu_model translation to type consistentIgor Mammedov
PPC handles -cpu FOO rather incosistently, i.e. it does case-insensitive matching of FOO to a CPU type (see: ppc_cpu_compare_class_name) but handles alias names as case-sensitive, as result: # qemu-system-ppc64 -M mac99 -cpu g3 qemu-system-ppc64: unable to find CPU model ' kN�U' # qemu-system-ppc64 -cpu 970MP_V1.1 qemu-system-ppc64: Unable to find sPAPR CPU Core definition while # qemu-system-ppc64 -M mac99 -cpu G3 # qemu-system-ppc64 -cpu 970MP_v1.1 start up just fine. Considering we can't take case-insensitive matching away, make it case-insensitive for all alias/type/core_type lookups. As side effect it allows to remove duplicate core types which are the same except of using different cased letters in name. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08PPC: KVM: Support machine option to set VSMT modeSam Bobroff
KVM now allows writing to KVM_CAP_PPC_SMT which has previously been read only. Doing so causes KVM to act, for that VM, as if the host's SMT mode was the given value. This is particularly important on Power 9 systems because their default value is 1, but they are able to support values up to 8. This patch introduces a way to control this capability via a new machine property called VSMT ("Virtual SMT"). If the value is not set on the command line a default is chosen that is, when possible, compatible with legacy systems. Note that the intialization of KVM_CAP_PPC_SMT has changed slightly because it has changed (in KVM) from a global capability to a VM-specific one. This won't cause a problem on older KVMs because VM capabilities fall back to global ones. Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08spapr: fallback to raw mode if best compat mode cannot be set during CASGreg Kurz
KVM PR doesn't allow to set a compat mode. This causes ppc_set_compat_all() to fail and we return H_HARDWARE to the guest right away. This is excessive: even if we favor compat mode since commit 152ef803ceb19, we should at least fallback to raw mode if the guest supports it. This patch modifies cas_check_pvr() so that it also reports that the real PVR was found in the table supplied by the guest. Note that this is only makes sense if raw mode isn't explicitely disabled (ie, the user didn't set the machine "max-cpu-compat" property). If this is the case, we can simply ignore ppc_set_compat_all() failures, and let the guest run in raw mode. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08hw/ppc/spapr_cpu_core: Add a proper check for spapr machineThomas Huth
QEMU currently crashes when the user tries to add a spapr-cpu-core on a non-pseries machine: $ qemu-system-ppc64 -S -machine ppce500,accel=tcg \ -device POWER5+_v2.1-spapr-cpu-core hw/ppc/spapr_cpu_core.c:178:spapr_cpu_core_realize_child: Object 0x55cee1f55160 is not an instance of type spapr-machine Aborted (core dumped) So let's add a proper check for the correct machine time with a more friendly error message here. Reported-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc4xx: Export ECB and PLB emulationBALATON Zoltan
Make these device models available outside ppc405_uc.c for reuse in 460EX emulation. They are left in their current place for now because they are used mostly unchanged and I'm not sure these correctly model the components in 440 SoCs (but they seem to be good enough). These functions could be moved in a subsequent clean up series when this is confirmed. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc4xx_i2c: Move to hw/i2cBALATON Zoltan
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc4xx_i2c: QOMifyBALATON Zoltan
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc4xx: Split off 4xx I2C emulation from ppc405_uc to its own fileBALATON Zoltan
This device appears in other SoCs as well not just in 405 ones and subsequent patches will modify it, so move it out of ppc405_uc.c in preparation Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc4xx: Make MAL emulation more genericBALATON Zoltan
Allow MAL with more RX and TX channels as found in newer versions. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc4xx: Move MAL from ppc405_uc to ppc4xx_devsBALATON Zoltan
This device appears in other SoCs as well not just in 405 ones Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08spapr_iommu: Realloc guest visible TCE table when hot(un)plugging vfio-pciAlexey Kardashevskiy
This replaces g_malloc() with spapr_tce_alloc_table() as this is the standard way of allocating tables and this allows moving the table back to KVM when unplugging a VFIO PCI device and VFIO TCE acceleration support is not present in the KVM. Although spapr_tce_alloc_table() is expected to fail with EBUSY if called when previous fd is not closed yet, in practice we will not see it because cap_spapr_vfio is false at the moment. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc: spapr: Make VCPU ID handling private to SPAPRSam Bobroff
The concept of a VCPU ID that differs from the CPU's index (cpu->cpu_index) exists only within SPAPR machines so, move the functions ppc_get_vcpu_id() and ppc_get_cpu_by_vcpu_id() into spapr.c and rename them appropriately. Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08ppc: spapr: Rename cpu_dt_id to vcpu_idSam Bobroff
This field actually records the VCPU ID used by KVM and, although the value is also used in the device tree it is primarily the VCPU ID so rename it as such. Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> [dwg: Updated comment missed in cpu.h] Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08e500: Use cpu_index instead of vcpu_dt_idSam Bobroff
The e500 platform code uses the function ppc_get_vcpu_dt_id() to get an id to put in its device tree. Which seems like it makes sense, but ppc_get_vcpu_dt_id() is actually badly named - it only differs from cpu_index in cases where you're running on KVM HV and the host's number of threads differs from the guests. Since KVM HV only supports PAPR, not e500, it doesn't make sense to use it here. Simply use the cpu_index instead (which is 'i' in this context because qemu_get_cpu(i) returns the cpu with cpu_index == i). Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> Reviewed-by: Greg Kurz <groug@kaod.org> [dwg: Rewrote commit message] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08spapr: add pseries-2.11 machine typeGreg Kurz
Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08spapr_iommu: unregister vmstate at unrealize timeGreg Kurz
Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-09-08spapr_iommu: pass object ownership to parent/ownerMichael Roth
TCE table objects attach themselves to an owner as a child property. unref afterward to allow them to be finalized when their owner is finalized. Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>