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2014-06-10apb: Fix compiler warnings (large constants)Stefan Weil
Both constants need more than 32 bit. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-06-05Merge remote-tracking branch 'remotes/mcayland/qemu-sparc' into stagingPeter Maydell
* remotes/mcayland/qemu-sparc: apb: implement IOMMU translation for PCI host bridge apb: handle reading/writing of IOMMU control registers apb: fix IOMMU register sizes apb: Move IOMMU registers into a separate IOMMUState struct tcx: move initialisation from realizefn to initfn tcx: move initialisation from SysBusDevice class to TCX class realizefn cg3: add extra check to prevent CG3 register array overflow cg3: move initialisation from realizefn to initfn Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-05apb: implement IOMMU translation for PCI host bridgeMark Cave-Ayland
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2014-06-05apb: handle reading/writing of IOMMU control registersMark Cave-Ayland
While the registers are documented as being 64-bit, Linux seems to access them in two halves as 2 x 32-bit accesses. Make sure that we can correctly handle this case. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2014-06-05apb: fix IOMMU register sizesMark Cave-Ayland
According to the referenced documentation, the IOMMU has 3 64-bit registers consisting of a control register, base register and flush register. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2014-06-05apb: Move IOMMU registers into a separate IOMMUState structMark Cave-Ayland
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2014-05-21pcie_host: Turn pcie_host_init() into an instance_initAndreas Färber
This assures the trivial field initialization is applied for any derived type - currently only Q35PCIHost. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-05-14savevm: Remove all the unneeded version_minimum_id_old (rest)Juan Quintela
After previous Peter patch, they are redundant. This way we don't assign them except when needed. Once there, there were lots of case where the ".fields" indentation was wrong: .fields = (VMStateField []) { and .fields = (VMStateField []) { Change all the combinations to: .fields = (VMStateField[]){ The biggest problem (appart from aesthetics) was that checkpatch complained when we copy&pasted the code from one place to another. Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2014-04-08hw/pci-host/prep: Don't reverse IO accesses on bigendian hostsPeter Maydell
The raven_io_read() and raven_io_write() functions pass and return values in little-endian format (since the IO op struct is marked DEVICE_LITTLE_ENDIAN); however they were storing the values in the buffer to pass to address_space_read/write() in host-endian order, which meant that on big-endian hosts the values were inadvertently reversed. Use the *_le_p() accessors instead so that we are consistent regardless of host endianness. Strictly speaking the byte order of the buffer for address_space_rw() is target byte order (which for PPC will be BE) but it doesn't actually matter as long as we are consistent about the marking on the IO op struct and which stl_*_p(). This bug was probably introduced due to confusion caused by the two different versions of ldl_p() and friends: bswap.h defines versions meaning "host endianness access" cpu-all.h defines versions meaning "target endianness access" As a target-independent source file prep.c gets the bswap.h versions; the very similar looking code in ioport.c is compiled per-target and gets the cpu-all.h versions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1396972271-22660-1-git-send-email-peter.maydell@linaro.org Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-03-27hw/pci-host/apb.c: Avoid shifting left into sign bitPeter Maydell
Add U suffix to avoid undefined behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-03-20raven: Use raven_ for all function prefixesHervé Poussineau
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2014-03-20raven: Fix PCI bus accesses with size > 1Hervé Poussineau
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2014-03-20raven: Add PCI bus mastering address spaceHervé Poussineau
This has been tested on Linux 2.4/PPC with the lsi53c895a SCSI adapter. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2014-03-20raven: Set a correct PCI memory regionHervé Poussineau
PCI memory region is 0x3f000000 bytes starting at 0xc0000000. However, keep compatibility with Open Hack'Ware expectations by adding a hack for Open Hack'Ware display. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2014-03-20raven: Set a correct PCI I/O memory regionHervé Poussineau
PCI I/O region is 0x3f800000 bytes starting at 0x80000000. Do not use global QEMU I/O region, which is only 64KB. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2014-03-20raven: Implement non-contiguous I/O regionHervé Poussineau
Remove now duplicated code from prep board. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2014-03-20raven: Rename intack region to pci_intackHervé Poussineau
Regions added subsequently will also have the pci_ prefix. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2014-03-13raven: Move BIOS loading from board code to PCI hostHervé Poussineau
Raven datasheet explains where firmware lives in system memory, so do it there instead of in board code. Other boards using the same PCI host will not have to copy the firmware loading code. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> [AF: Drop BIOS size workaround in favor of replacing our firmware blob] Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2014-03-11q35: Correct typo BRDIGE -> BRIDGEBALATON Zoltan
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-03-09pam: partly fix write-only modeHervé Poussineau
In write-only mode, writes are forwarded to RAM, while reads should not be handled (ie should return 0xff). Assume that in this mode, no read access is ever done, as they shouldn't give any sensible result. So, in write-only mode, alias PAM region to RAM, instead of PCI memory (which can even be mapped to some device!) This fixes Award BIOS, which use this mode to shadow system BIOS and video BIOS. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-02-13Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
acpi,pc,pci fixes and enhancements Most changes here are hotplug related: This merges hotplug infrastructure changes by Igor, some acpi related fixes, and PC fixes. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Mon 10 Feb 2014 09:13:26 GMT using RSA key ID D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: ACPI: Remove commented-out code from HPET._CRS hw/pci: switch to a generic hotplug handling for PCIDevice pci/pcie: convert PCIE hotplug to use hotplug-handler API pci/shpc: convert SHPC hotplug to use hotplug-handler API acpi/piix4pm: convert ACPI PCI hotplug to use hotplug-handler API qdev:pci: refactor PCIDevice to use generic "hotpluggable" property hw/acpi: move typeinfo to the file end qdev: add "hotpluggable" property to Device qdev: add to BusState "hotplug-handler" link define hotplug interface loader: document that errno is set pc.c: better error message on initrd sizing failure pc_piix: enable legacy hotplug for Xen qtest: don't report signals if qtest driver enabled hw:piix4:acpi: reuse pcihp code for legacy PCI hotplug pcihp: remove unused AcpiPciHpPciStatus.device_present field pcihp: make pci_read() mmio calback compatible with legacy ACPI hotplug pcihp: make PCI hotplug mmio handlers indifferent to PCI_HOTPLUG_ADDR pcihp: replace enable|disable_device() with oneliners pcihp: reduce number of device check events Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-10qdev:pci: refactor PCIDevice to use generic "hotpluggable" propertyIgor Mammedov
Get rid of PCIDevice specific PCIDeviceClass.no_hotplug and use generic DeviceClass.hotpluggable field instead. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-02-09raven: Use constant PCI_NUM_PINS instead of 4Hervé Poussineau
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2014-01-10Merge remote-tracking branch 'mst/tags/for_anthony' into stagingAnthony Liguori
acpi,pci,pc,fedora,virtio fixes and enhancements This includes some Preparatory patches for cpu hotplug for q25 and memory hotplug by Igor, tests and memory mapping change by Laszlo and pci reset cleanup by Paolo. There are also some fixes for fedora and virtio: included here since they are test blockers for me. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Mon 23 Dec 2013 08:07:18 AM PST using RSA key ID D28D5469 # gpg: Can't check signature: public key not found * mst/tags/for_anthony: target-arm: fix build with gcc 4.8.2 virtio: add back call to virtio_bus_device_unplugged piix: fix 32bit pci hole qdev: switch reset to post-order qdev: allow both pre- and post-order vists in qdev walking functions pci: clean up resetting of IRQs pci: do not export pci_bus_reset ACPI/DSDT-CPU: cleanup bogus comment ACPI: Q35 DSDT: fix CPU hotplug GPE0.2 handler acpi: ich9: allow guest to clear SCI rised by GPE acpi: factor out common pm_update_sci() into acpi core acpi: piix4: remove not needed GPE0 mask i440fx-test: verify firmware under 4G and 1M, both -bios and -pflash i440fx-test: generate temporary firmware blob i440fx-test: give each GTest case its own qtest i440fx-test: qtest_start() should be paired with qtest_end() hw/i386/pc_sysfw: support two flash drives pc_piix: document gigabyte_align piix: gigabyte alignment for ram Message-id: 1387815007-1272-1-git-send-email-mst@redhat.com Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-12-23piix: fix 32bit pci holeGerd Hoffmann
Make the 32bit pci hole start at end of ram, so all possible address space is covered. We used to try and make addresses aligned so they are easier to cover with MTRRs, but since they are cosmetic on KVM, this is probably not worth worrying about. Of course the firmware can use less than that. Leaving space unused is no problem, mapping pci bars outside the hole causes problems though. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23piix3 piix4: Clean up use of cannot_instantiate_with_device_add_yetMarkus Armbruster
A PIIX3/PIIX4 southbridge has multiple functions. We model each function as a separate qdev. Two of them need some special wiring set up in pc_init1() or mips_malta_init() to work: the ISA bridge at 01.0, and the SMBus controller at 01.3. The IDE controller at 01.1 (piix3-ide, piix3-ide-xen, piix4-ide) has always had cannot_instantiate_with_device_add_yet set, but there is no obvious reason why device_add could not work for them. Drop it. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-12-23pci-host: Consistently set cannot_instantiate_with_device_add_yetMarkus Armbruster
Many PCI host bridges consist of a sysbus device and a PCI device. You need both for the thing to work. Arguably, these bridges should be modelled as a single, composite devices instead of pairs of seemingly independent devices you can only use together, but we're not there, yet. Since the sysbus part can't be instantiated with device_add, yet, permitting it with the PCI part is useless. We shouldn't offer useless options to the user, so let's set cannot_instantiate_with_device_add_yet for them. It's already set for Bonito, Grackle, i440FX and Raven. Document why. Set it for the others: dec-21154, e500-host-bridge, gt64120_pci, mch, pbm-pci, ppc4xx-host-bridge, sh_pci_host, u3-agp, uni-north-agp, uni-north-internal-pci, uni-north-pci, and versatile_pci_host. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-12-23sysbus: Set cannot_instantiate_with_device_add_yetMarkus Armbruster
device_add plugs devices into suitable bus. For "real" buses, that actually connects the device. For sysbus, the connections need to be made separately, and device_add can't do that. The device would be left unconnected, and could not possibly work. Quite a few, but not all sysbus devices already set cannot_instantiate_with_device_add_yet in their class init function. Set it in their abstract base's class init function sysbus_device_class_init(), and remove the now redundant assignments from device class init functions. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-12-23qdev: Replace no_user by cannot_instantiate_with_device_add_yetMarkus Armbruster
In an ideal world, machines can be built by wiring devices together with configuration, not code. Unfortunately, that's not the world we live in right now. We still have quite a few devices that need to be wired up by code. If you try to device_add such a device, it'll fail in sometimes mysterious ways. If you're lucky, you get an unmysterious immediate crash. To protect users from such badness, DeviceClass member no_user used to make device models unavailable with -device / device_add, but that regressed in commit 18b6dad. The device model is still omitted from help, but is available anyway. Attempts to fix the regression have been rejected with the argument that the purpose of no_user isn't clear, and it's prone to misuse. This commit clarifies no_user's purpose. Anthony suggested to rename it cannot_instantiate_with_device_add_yet_due_to_internal_bugs, which I shorten somewhat to keep checkpatch happy. While there, make it bool. Every use of cannot_instantiate_with_device_add_yet gets a FIXME comment asking for rationale. The next few commits will clean them all up, either by providing a rationale, or by getting rid of the use. With that done, the regression fix is hopefully acceptable. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-12-20PPC: Use default pci bus name for grackle and heathrowAlexander Graf
There's no good reason to call our bus "pci" rather than let the default bus name take over ("pci.0"). The big downside to calling it different from anyone else is that tools that pass -device get confused. They are looking for a bus "pci.0" rather than "pci". To make life easier for everyone, let's just drop the name override. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-10pc: map PCI address space as catchall region for not mapped addressesMichael S. Tsirkin
With a help of negative memory region priority PCI address space is mapped underneath RAM regions effectively catching every access to addresses not mapped by any other region. It simplifies PCI address space mapping into system address space. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Igor Mammedov <imammedo@redhat.com>
2013-11-10Fix pc migration from qemu <= 1.5Cole Robinson
The following commit introduced a migration incompatibility: commit 568f0690fd9aa4d39d84b04c1a5dbb53a915c3fe Author: David Gibson <david@gibson.dropbear.id.au> Date: Thu Jun 6 18:48:49 2013 +1000 pci: Replace pci_find_domain() with more general pci_root_bus_path() The issue is that i440fx savevm idstr went from 0000:00:00.0/I440FX to 0000:00.0/I440FX. Unfortunately we are stuck with the breakage for 1.6 machine types. Add a compat property to maintain the busted idstr for the 1.6 machine types, but revert to the old style format for 1.7+, and <= 1.5. Tested with migration from qemu 1.5, qemu 1.6, and qemu.git. Cc: qemu-stable@nongnu.org Signed-off-by: Cole Robinson <crobinso@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-10-31Merge remote-tracking branch 'mst/tags/for_anthony' into stagingAnthony Liguori
pci, pc, acpi fixes, enhancements This includes some pretty big changes: - pci master abort support by Marcel - pci IRQ API rework by Marcel - acpi generation support by myself Everything has gone through several revisions, latest versions have been on list for a while without any more comments, tested by several people. Please pull for 1.7. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Tue 15 Oct 2013 07:33:48 AM CEST using RSA key ID D28D5469 # gpg: Can't check signature: public key not found * mst/tags/for_anthony: (39 commits) ssdt-proc: update generated file ssdt: fix PBLK length i386: ACPI table generation code from seabios pc: use new api to add builtin tables acpi: add interface to access user-installed tables hpet: add API to find it pvpanic: add API to access io port ich9: APIs for pc guest info piix: APIs for pc guest info acpi/piix: add macros for acpi property names i386: define pc guest info loader: allow adding ROMs in done callbacks i386: add bios linker/loader loader: use file path size from fw_cfg.h acpi: ssdt pcihp: updat generated file acpi: pre-compiled ASL files acpi: add rules to compile ASL source i386: add ACPI table files from seabios q35: expose mmcfg size as a property q35: use macro for MCFG property name ... Message-id: 1381818560-18367-1-git-send-email-mst@redhat.com Signed-off-by: Anthony Liguori <anthony@codemonkey.ws>
2013-10-14ich9: APIs for pc guest infoMichael S. Tsirkin
This adds APIs that will be used to fill in acpi tables, implemented using QOM, to various ich9 components. Some information is still missing in QOM, so we fall back on lookups by type instead. Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Tested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-10-14piix: APIs for pc guest infoMichael S. Tsirkin
This adds APIs that will be used to fill in guest acpi tables. Some required information is still lacking in QOM, so we fall back on lookups by type and returning explicit types. Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Tested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-10-14q35: expose mmcfg size as a propertyMichael S. Tsirkin
Address is already exposed, expose size for symmetry. Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Tested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-10-14q35: use macro for MCFG property nameMichael S. Tsirkin
Useful to make it accessible through QOM. Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Tested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-09-30Merge remote-tracking branch 'mst/tags/for_anthony' into stagingAnthony Liguori
pc,pci,virtio fixes and cleanups This includes pc and pci cleanups and enhancements, and a virtio-net bugfix related to softmac programming. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Sun 29 Sep 2013 01:51:16 AM CDT using RSA key ID D28D5469 # gpg: Can't check signature: public key not found # By Michael S. Tsirkin (8) and others # Via Michael S. Tsirkin * mst/tags/for_anthony: smbios: Factor out smbios_maybe_add_str() smbios: Make multiple -smbios type= accumulate sanely smbios: Improve diagnostics for conflicting entries smbios: Convert to QemuOpts smbios: Normalize smbios_entry_add()'s error handling to exit(1) virtio-net: fix up HMP NIC info string on reset pci: remove explicit check to 64K ioport size piix4: disable io on reset piix: use 64 bit window programmed by guest q35: use 64 bit window programmed by guest pci: add helper to retrieve the 64-bit range range: add min/max operations on ranges range: add Range to typedefs q35: make pci window address/size match guest cfg Message-id: 1380437951-21788-1-git-send-email-mst@redhat.com
2013-09-20q35: Fix typo in constant DEFUALT -> DEFAULT.Richard W.M. Jones
Signed-off-by: Richard W.M. Jones <rjones@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-09-15piix: use 64 bit window programmed by guestMichael S. Tsirkin
Detect the 64 bit window programmed by firmware and configure properties accordingly. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-09-15q35: use 64 bit window programmed by guestMichael S. Tsirkin
Detect the 64 bit window programmed by firmware and configure properties accordingly. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-09-15q35: make pci window address/size match guest cfgMichael S. Tsirkin
For Q35, MMCFG address and size are guest configurable. Update w32 property to make it behave accordingly. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-09-03Merge remote-tracking branch 'mst/tags/for_anthony' into stagingAnthony Liguori
pc,pci,virtio fixes and cleanups This includes pc and pci cleanups and enhancements, and a virtio bugfix for level interrupts. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Sun 01 Sep 2013 03:15:36 AM CDT using RSA key ID D28D5469 # gpg: Can't check signature: public key not found # By Michael S. Tsirkin (3) and others # Via Michael S. Tsirkin * mst/tags/for_anthony: virtio_pci: fix level interrupts with irqfd pc: reduce duplication, fix PIIX descriptions hw: Clean up bogus default boot order pci: add config space access traces pc: fix regression for 64 bit PCI memory pci: Introduce helper to retrieve a PCI device's DMA address space Message-id: 1378023590-11109-1-git-send-email-mst@redhat.com Signed-off-by: Anthony Liguori <anthony@codemonkey.ws>
2013-08-30qom: Pass available size to object_initialize()Andreas Färber
To be passed on to object_initialize_with_type(). Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> (virtio-ccw) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-08-30pci: Pass size to pci_bus_new_inplace()Andreas Färber
To be passed to qbus_create_inplace(). Reviewed-by: Wenchao Xia <xiawenc@linux.vnet.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-08-27pc: fix regression for 64 bit PCI memoryMichael S. Tsirkin
commit 398489018183d613306ab022653552247d93919f pc: limit 64 bit hole to 2G by default introduced a way for management to control the window allocated to the 64 bit PCI hole. This is useful, but existing management tools do not know how to set this property. As a result, e.g. specifying a large ivshmem device with size > 4G is broken by default. For example this configuration no longer works: -device ivshmem,size=4294967296,chardev=cfoo -chardev socket,path=/tmp/sock,id=cfoo,server,nowait Fix this by detecting that hole size was not specified and defaulting to the backwards-compatible value of 1 << 62. Cc: qemu-stable@nongnu.org Cc: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-07-31pci-host/prep: Set isa_mem_base in the PCI host bridgeHervé Poussineau
Currently, it is done by i82378 PCI-ISA bridge, which shouldn't care about it. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2013-07-29pc: limit 64 bit hole to 2G by defaultIgor Mammedov
It turns out that some 32 bit windows guests crash if 64 bit PCI hole size is >2G. Limit it to 2G for piix and q35 by default. User may override default 64-bit PCI hole size by using "pci-hole64-size" property. Examples: -global i440FX-pcihost.pci-hole64-size=4G -global q35-pcihost.pci-hole64-size=4G Reported-by: Igor Mammedov <imammedo@redhat.com>, Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Message-id: 1375109277-25561-8-git-send-email-imammedo@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29pc: replace i440fx_common_init() with i440fx_init()Igor Mammedov
It isn't used anywhere else. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Message-id: 1375109277-25561-4-git-send-email-imammedo@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29pc: add I440FX QOM cast macroIgor Mammedov
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Message-id: 1375109277-25561-3-git-send-email-imammedo@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-23 08:25:32 +0000