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path: root/hw/pci-host/apb.c
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2014-09-09apb: implement PCI bus error interrupt map registersMark Cave-Ayland
Both OpenBSD and FreeBSD SPARC64 attempt to read the interrupt map from the hardware and will fail if the correct ino isn't present. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2014-08-28iommu: add is_write as a parameter to the translate function of ↵Le Tan
MemoryRegionIOMMUOps Add a bool variable is_write as a parameter to the translate function of MemoryRegionIOMMUOps to indicate the operation of the access. It can be used for correct fault reporting from within the callback. Change the interface of related functions. Signed-off-by: Le Tan <tamlokveer@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2014-08-17apb: add IOMMU flush register implementationMark Cave-Ayland
The IOMMU flush register is a write-only register used to remove entries from the hardware TLB. Allow guest writes to this register as a no-op, and return a value of 0 for reads. This fixes IOMMU DMA operations under NetBSD SPARC64. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2014-06-20apb: Fix out-of-bounds array write accessStefan Weil
The array regs is declared with IOMMU_NREGS (3) elements and accessed using IOMMU_CTRL (0) and IOMMU_BASE (8). In most cases, those values are right shifted before being used as an index which results in indices 0 and 1. In one case, this right shift was missing for IOMMU_BASE which results in an out-of-bounds write access with index 8. The patch adds the missing shift operation also for IOMMU_CTRL where it is needed only for cosmetic reasons. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2014-06-10apb: Fix compiler warnings (large constants)Stefan Weil
Both constants need more than 32 bit. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-06-05apb: implement IOMMU translation for PCI host bridgeMark Cave-Ayland
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2014-06-05apb: handle reading/writing of IOMMU control registersMark Cave-Ayland
While the registers are documented as being 64-bit, Linux seems to access them in two halves as 2 x 32-bit accesses. Make sure that we can correctly handle this case. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2014-06-05apb: fix IOMMU register sizesMark Cave-Ayland
According to the referenced documentation, the IOMMU has 3 64-bit registers consisting of a control register, base register and flush register. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2014-06-05apb: Move IOMMU registers into a separate IOMMUState structMark Cave-Ayland
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2014-03-27hw/pci-host/apb.c: Avoid shifting left into sign bitPeter Maydell
Add U suffix to avoid undefined behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-12-23pci-host: Consistently set cannot_instantiate_with_device_add_yetMarkus Armbruster
Many PCI host bridges consist of a sysbus device and a PCI device. You need both for the thing to work. Arguably, these bridges should be modelled as a single, composite devices instead of pairs of seemingly independent devices you can only use together, but we're not there, yet. Since the sysbus part can't be instantiated with device_add, yet, permitting it with the PCI part is useless. We shouldn't offer useless options to the user, so let's set cannot_instantiate_with_device_add_yet for them. It's already set for Bonito, Grackle, i440FX and Raven. Document why. Set it for the others: dec-21154, e500-host-bridge, gt64120_pci, mch, pbm-pci, ppc4xx-host-bridge, sh_pci_host, u3-agp, uni-north-agp, uni-north-internal-pci, uni-north-pci, and versatile_pci_host. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29pci-bridge: Turn PCIBridge into abstract QOM typeAndreas Färber
Introduce TYPE_PCI_BRIDGE as base type and use PCI_BRIDGE() casts. Reviewed-by: Don Koch <dkoch@verizon.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> [AF: Updated pbm-bridge parent to TYPE_PCI_BRIDGE] Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29devices: Associate devices to their logical categoryMarcel Apfelbaum
The category will be used to sort the devices displayed in the command line help. Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com> Message-id: 1375107465-25767-4-git-send-email-marcel.a@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25sparc64: unbreakPaolo Bonzini
... by making apb a subclass of TYPE_PCI_HOST_BRIDGE. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-21-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25sparc64: remove indirection for I/O port accessPaolo Bonzini
This fixes endianness bugs in I/O port access. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-13-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-04hw/p*: pass owner to memory_region_init* functionsPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-07-04memory: add owner argument to initialization functionsPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-27sparc64: use direct interrupt mapping for PCI devicesArtyom Tarasenko
Every PCI Slot in PBM has 4 directly mapped IRQ lines. Use the IRQ routing schema 0bssnn (Bus, Slot, interrupt Number) described in Section 19.3.3 of UltraSPARC™-IIi User's Manual. Please note that this patch requires the OpenBIOS counterpart patch. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-04-27sparc64: fix loosing interruptsArtyom Tarasenko
- clear interrupts only on writing to the interrupt clear registers - don't overwrite a currently active interrupt request - use the correct addresses for the interrupt clear registers (section 19.3.3.3 of the UltraSPARC™-IIi User’s Manual) Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-04-27sparc64: allow 64 IRQ linesArtyom Tarasenko
According to UltraSPARC™-IIi User’s Manual, PBM has 64 IRQ lines. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-04-08hw: move PCI bridges to hw/pci-* or hw/ARCHPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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