aboutsummaryrefslogtreecommitdiff
path: root/hw/pci-bridge/cxl_downstream.c
AgeCommit message (Expand)Author
2023-11-07hw/pci-bridge/cxl_downstream: Set default link width and link speedJonathan Cameron
2023-11-07hw/cxl/mbox: Add Physical Switch Identify command.Jonathan Cameron
2023-11-07hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExtJonathan Cameron
2023-09-20hw/pci: spelling fixesMichael Tokarev
2023-03-02hw/pci-bridge/cxl_downstream: Fix type naming mismatchJonathan Cameron
2022-12-21pci: drop redundant PCIDeviceClass::is_bridge fieldIgor Mammedov
2022-06-16pci-bridge/cxl_downstream: Add a CXL switch downstream portJonathan Cameron