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2011-09-23hw/omap_gpmc: Modify correct field when writing IRQSTATUS registerPeter Maydell
Writing to IRQSTATUS should affect irqst, not irqen -- error spotted by Andrzej Zaborowski. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-09-23hw/omap_gpmc: Add comment about FIFOTHRESHOLDSTATUS bitPeter Maydell
Promote the remark about why we handle FIFOTHRESHOLDSTATUS the way we do from the commit message of de8af7fe0 to a comment in the code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-08-28omap_gpmc: Implement prefetch enginePeter Maydell
This commit implements the prefetch engine feature of the GPMC which can be used for NAND devices. This includes both interrupt driven and DMA-filling modes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-08-28omap: Wire up the DMA request line to the GPMCPeter Maydell
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-08-28omap_gpmc: Pull prefetch engine data into sub-structPeter Maydell
Refactor the gpmc state structure so items relating to the prefetch engine are in their own sub-struct and have more useful names. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-08-28omap_gpmc: Accept a zero mask field on omap3630Juha Riihimäki
OMAP3630 adds an extra bit of address masking, so a mask of 0xb1111 is valid. Unfortunately the GPMC_REVISION is the same as on the OMAP3430 which only has three bits of address masking, so we have to derive this feature directly from the OMAP revision rather than from the GPMC revision. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> [Riku Voipio: Fixes and restructuring patchset] Signed-off-by: Riku Voipio <riku.voipio@iki.fi> [Peter Maydell: More fixes and cleanups for upstream submission] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-08-28omap_gpmc: Support NAND devicesPeter Maydell
Support accesses to NAND devices, both by mapping them into the GPMC address space, and via the NAND_COMMAND, NAND_ADDRESS and NAND_DATA GPMC registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-08-28omap_gpmc: Reindent misindented switch statementsPeter Maydell
Whitespace-only change fixing indentation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-08-28omap_gpmc: Calculate revision from OMAP modelJuha Riihimäki
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> [Riku Voipio: Fixes and restructuring patchset] Signed-off-by: Riku Voipio <riku.voipio@iki.fi> [Peter Maydell: More fixes and cleanups for upstream submission] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-08-28omap_gpmc: Take omap_mpu_state* in omap_gpmc_initJuha Riihimäki
Take a pointer to the omap mpu state struct in omap_gpmc_init. Some details of GPMC behaviour depend on the OMAP version we are a part of. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> [Riku Voipio: Fixes and restructuring patchset] Signed-off-by: Riku Voipio <riku.voipio@iki.fi> [Peter Maydell: More fixes and cleanups for upstream submission] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-08-28omap_gpmc: Fix handling of FIFOTHRESHOLDSTATUS bitPeter Maydell
The OMAP3 TRM is inconsistent about whether the GPMC FIFOTHRESHOLDSTATUS bit should be set when FIFOPOINTER > FIFOTHRESHOLD or when it is >= FIFOTHRESHOLD. Apparently the underlying functional spec from which the TRM was created states that the behaviour is ">=", and this also makes more conceptual sense. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-08-28omap_gpmc: Wire up the GPMC IRQ correctlyPeter Maydell
The omap_gpmc wasn't actually wiring up its IRQ, so anything that provoked an interrupt would be using uninitialised data for its IRQ number. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-08-28omap_gpmc: GPMC_IRQSTATUS is write-one-to-clearPeter Maydell
Fix a bug in the handling of writes to GPMC_IRQSTATUS: it behaves as "write one to clear, writing zero is ignored". Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-08-28omap_gpmc: Refactor omap_gpmc_cs_map and omap_gpmc_cs_unmapPeter Maydell
Refactor the omap_gpmc_cs_map/unmap functions: * take the omap_gpmc_s* and a chipselect id rather than the omap_gpmc_cs_file_s*, so they have access to the general gpmc member fields * extract the base and mask from the config registers in the functions rather than at every callsite * check for CSVALID in the functions rather than at every callsite Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-08-28omap_gpmc: Clean up omap_gpmc_attach MemoryRegion conversionPeter Maydell
Now that all callers of omap_gpmc_attach pass in a MemoryRegion*, we can remove the base_update and unmap function pointer arguments, and the opaque pointer that was passed into these callbacks. We can also remove the base and size fields from omap_gpmc_cs_file_s as these are no longer necessary (you don't need the base/size to unmap a MemoryRegion the way you did to undo a mapping made with cpu_register_physical_memory()). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-08-23hw/omap_gpmc: Don't try to map CS0 twice on resetPeter Maydell
Remove a spurious second map of the OMAP GPMC CS0 region on reset. This fixes an assertion failure when we try to add the region to its container when it was already added. (The old code did not complain about mismatched map/unmap calls, but the new MemoryRegion implementation does.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-08-22omap_gpmc/nseries/tusb6010: convert to memory APIAvi Kivity
Somewhat clumsy since it needs a variable sized region. Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-08-20Use glib memory allocation and free functionsAnthony Liguori
qemu_malloc/qemu_free no longer exist after this commit. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-12-11Add endianness as io mem parameterAlexander Graf
As stated before, devices can be little, big or native endian. The target endianness is not of their concern, so we need to push things down a level. This patch adds a parameter to cpu_register_io_memory that allows a device to choose its endianness. For now, all devices simply choose native endian, because that's the same behavior as before. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-30hw/omap2.c : separate gpmc(general purpose memory controller)cmchao
Signed-off-by: cmchao <cmchao@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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