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2023-11-21net: Provide MemReentrancyGuard * to qemu_new_nic()Akihiko Odaki
Recently MemReentrancyGuard was added to DeviceState to record that the device is engaging in I/O. The network device backend needs to update it when delivering a packet to a device. In preparation for such a change, add MemReentrancyGuard * as a parameter of qemu_new_nic(). Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-11-15hw/net/cadence_gem.c: spelling fixes: OctectsMichael Tokarev
Fixes: c755c943aa2e "hw/net/cadence_gem: use REG32 macro for register definitions" Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Luc Michel <luc.michel@amd.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2023-11-13igb: Add Function Level Reset to PF and VFCédric Le Goater
The Intel 82576EB GbE Controller say that the Physical and Virtual Functions support Function Level Reset. Add the capability to the PF device model using device property "x-pcie-flr-init" which is "on" by default and "off" for machines <= 8.1 to preserve compatibility. The FLR capability of the VF model is defined according to the FLR property of the PF, this to avoid adding an extra compatibility property. Cc: Sriram Yagnaraman <sriram.yagnaraman@est.tech> Fixes: 3a977deebe6b ("Intrdocue igb device emulation") Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com> Signed-off-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-11-13igb: Add a VF reset handlerCédric Le Goater
Export the igb_vf_reset() helper routine from the PF model to let the IGBVF model implement its own device reset. Cc: Akihiko Odaki <akihiko.odaki@daynix.com> Suggested-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-11-07hw/xen: update Xen PV NIC to XenDevice modelDavid Woodhouse
This allows us to use Xen PV networking with emulated Xen guests, and to add them on the command line or hotplug. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org>
2023-11-01migration: Use vmstate_register_any()Juan Quintela
This are the easiest cases, where we were already using VMSTATE_INSTANCE_ID_ANY. Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <20231020090731.28701-3-quintela@redhat.com>
2023-10-27hw/net/cadence_gem: enforce 32 bits variable size for CRCLuc Michel
The CRC was stored in an unsigned variable in gem_receive. Change it for a uint32_t to ensure we have the correct variable size here. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-12-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/net/cadence_gem: perform PHY access on write onlyLuc Michel
The MDIO access is done only on a write to the PHYMNTNC register. A subsequent read is used to retrieve the result but does not trigger an MDIO access by itself. Refactor the PHY access logic to perform all accesses (MDIO reads and writes) at PHYMNTNC write time. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-11-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fieldsLuc Michel
Use the FIELD macro to describe the PHYMNTNC register fields. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-10-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/net/cadence_gem: use FIELD to describe DESCONF6 register fieldsLuc Michel
Use the FIELD macro to describe the DESCONF6 register fields. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20231017194422.4124691-9-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/net/cadence_gem: use FIELD to describe IRQ register fieldsLuc Michel
Use de FIELD macro to describe the IRQ related register fields. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-8-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fieldsLuc Michel
Use de FIELD macro to describe the TXSTATUS and RXSTATUS register fields. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-7-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/net/cadence_gem: use FIELD to describe DMACFG register fieldsLuc Michel
Use de FIELD macro to describe the DMACFG register fields. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-6-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/net/cadence_gem: use FIELD to describe NWCFG register fieldsLuc Michel
Use de FIELD macro to describe the NWCFG register fields. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-5-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/net/cadence_gem: use FIELD to describe NWCTRL register fieldsLuc Michel
Use the FIELD macro to describe the NWCTRL register fields. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-4-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/net/cadence_gem: use FIELD for screening registersLuc Michel
Describe screening registers fields using the FIELD macros. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-3-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/net/cadence_gem: use REG32 macro for register definitionsLuc Michel
Replace register defines with the REG32 macro from registerfields.h in the Cadence GEM device. Signed-off-by: Luc Michel <luc.michel@amd.com> Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-2-luc.michel@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-20Merge tag 'migration-20231020-pull-request' of ↵Stefan Hajnoczi
https://gitlab.com/juan.quintela/qemu into staging Migration Pull request (20231020) In this pull request: - disable analyze-migration on s390x (thomas) - Fix parse_ramblock() (peter) - start merging live update (steve) - migration-test support for using several binaries (fabiano) - multifd cleanups (fabiano) CI: https://gitlab.com/juan.quintela/qemu/-/pipelines/1042492801 Please apply. # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEGJn/jt6/WMzuA0uC9IfvGFhy1yMFAmUyJMsACgkQ9IfvGFhy # 1yP0AQ/9ELr6VJ0crqzfGm2dy2emnZMaQhDtzR4Kk4ciZF6U+GiATdGN9hK499mP # 6WzRIjtSzwD8YZvhLfegxIVTGcEttaM93uXFPznWrk7gwny6QTvuA4qtcRYejTSl # wE4GQQOsSrukVCUlqcZtY/t2aphVWQzlx8RRJE3XGaodT1gNLMjd+xp34NbbOoR3 # 32ixpSPUCOGvCd7hb+HG7pEzk+905Pn2URvbdiP71uqhgJZdjMAv8ehSGD3kufdg # FMrZyIEq7Eguk2bO1+7ZiVuIafXXRloIVqi1ENmjIyNDa/Rlv2CA85u0CfgeP6qY # Ttj+MZaz8PIhf97IJEILFn+NDXYgsGqEFl//uNbLuTeCpmr9NPhBzLw8CvCefPrR # rwBs3J+QbDHWX9EYjk6QZ9QfYJy/DXkl0KfdNtQy9Wf+0o1mHDn5/y3s782T24aJ # lGo0ph4VJLBNOx58rpgmoO5prRIjqzF5w4j8pCSeGUC4Bcub5af4TufYrwaf+cps # iIbNFx79dLXBlfkKIn7i9RLpz7641Fs/iTQ/MZh1eyvX++UDXAPWnbd4GDYOEewA # U3WKsTs/ipIbY8nqaO4j1VMzADPUfetBXznBw60xsZcfjynFJsPV6/F/0OpUupdv # qPEY4LZ2uwP4K7AlzrUzUn2f3BKrspL0ObX0qTn0WJ8WX5Jp/YA= # =m+uB # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Oct 2023 23:57:15 PDT # gpg: using RSA key 1899FF8EDEBF58CCEE034B82F487EF185872D723 # gpg: Good signature from "Juan Quintela <quintela@redhat.com>" [full] # gpg: aka "Juan Quintela <quintela@trasno.org>" [full] # Primary key fingerprint: 1899 FF8E DEBF 58CC EE03 4B82 F487 EF18 5872 D723 * tag 'migration-20231020-pull-request' of https://gitlab.com/juan.quintela/qemu: tests/qtest: Don't print messages from query instances tests/qtest/migration: Allow user to specify a machine type tests/qtest/migration: Support more than one QEMU binary tests/qtest/migration: Set q35 as the default machine for x86_86 tests/qtest/migration: Specify the geometry of the bootsector tests/qtest/migration: Define a machine for all architectures tests/qtest/migration: Introduce find_common_machine_version tests/qtest: Introduce qtest_resolve_machine_alias tests/qtest: Introduce qtest_has_machine_with_env tests/qtest: Allow qtest_get_machines to use an alternate QEMU binary tests/qtest: Introduce qtest_init_with_env tests/qtest: Allow qtest_qemu_binary to use a custom environment variable migration/multifd: Stop checking p->quit in multifd_send_thread migration: simplify notifiers migration: Fix parse_ramblock() on overwritten retvals migration: simplify blockers tests/qtest/migration-test: Disable the analyze-migration.py test on s390x Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-20Merge tag 'C3700-pull-request' of https://github.com/hdeller/qemu-hppa into ↵Stefan Hajnoczi
staging target/hppa: Add emulation of a C3700 HP-PARISC workstation This series adds a new PA-RISC machine emulation for the HP-PARISC C3700 workstation. The physical HP C3700 machine has a PA2.0 (64-bit) CPU, in contrast to the existing emulation of a B160L workstation which is a 32-bit only machine and where it's Dino PCI controller isn't 64-bit capable. With the HP C3700 machine emulation (together with the emulated Astro Memory controller and the Elroy PCI bridge) it's now possible to enhance the hppa CPU emulation to support the 64-bit instruction set in upcoming patches. Helge v4 changes: - Fix testsuite error in astro by adding a realize() implementation v3 changes: based on feedback from BALATON Zoltan <balaton@eik.bme.hu>: - apply paches in different order to bring them logically closer to each other - update comments in lasips2 - rephrased title and commit message of MAINTAINERS patch v2 changes: suggestions by BALATON Zoltan <balaton@eik.bme.hu>: - merged pci_ids and tulip patch - dropped comments in lasips2 - mention additional cleanups in patch "Require at least SeaBIOS-hppa version 10" suggestions by Philippe Mathieu-Daudé <philmd@linaro.org>: - dropped static pci_bus variable # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCZTGzDQAKCRD3ErUQojoP # X9psAP0cHfTuJuXMiBWhrJhfp5VV0TURvaNXjCGyK8qvfbK+zgEArg3nvKhZPvnu # jVSq6b/Ppf3eCAZIYSVIsfLITbElTQ4= # =Esj+ # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Oct 2023 15:51:57 PDT # gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F # gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown] # gpg: aka "Helge Deller <deller@kernel.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603 # Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F * tag 'C3700-pull-request' of https://github.com/hdeller/qemu-hppa: hw/hppa: Add new HP C3700 machine hw/hppa: Split out machine creation hw/hppa: Provide RTC and DebugOutputPort on CPU #0 hw/hppa: Export machine name, BTLBs, power-button address via fw_cfg MAINTAINERS: Update HP-PARISC entries pci-host: Wire up new Astro/Elroy PCI bridge hw/pci-host: Add Astro system bus adapter found on PA-RISC machines lasips2: LASI PS/2 devices are not user-createable pci_ids/tulip: Add PCI vendor ID for HP and use it in tulip hw/hppa: Require at least SeaBIOS-hppa version 10 target/hppa: Update to SeaBIOS-hppa version 10 Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-20migration: simplify notifiersSteve Sistare
Pass the callback function to add_migration_state_change_notifier so that migration can initialize the notifier on add and clear it on delete, which simplifies the call sites. Shorten the function names so the extra arg can be added more legibly. Hide the global notifier list in a new function migration_call_notifiers, and make it externally visible so future live update code can call it. No functional change. Signed-off-by: Steve Sistare <steven.sistare@oracle.com> Reviewed-by: Peter Xu <peterx@redhat.com> Tested-by: Michael Galaxy <mgalaxy@akamai.com> Reviewed-by: Michael Galaxy <mgalaxy@akamai.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-ID: <1686148954-250144-1-git-send-email-steven.sistare@oracle.com>
2023-10-19hw/net: Declare link using static DEFINE_PROP_LINK() macroPhilippe Mathieu-Daudé
Declare link statically using DEFINE_PROP_LINK(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20231017140150.44995-7-philmd@linaro.org>
2023-10-17pci_ids/tulip: Add PCI vendor ID for HP and use it in tulipHelge Deller
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-06hw/net/vhost_net: Silence compiler warning when compiling with -WshadowThomas Huth
Rename the innermost local variables to avoid compiler warnings with "-Wshadow". Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20231004084939.96349-1-thuth@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2023-10-05Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Stefan Hajnoczi
into staging virtio,pci: features, cleanups vdpa: shadow vq vlan support net migration with cvq cxl: support emulating 4 HDM decoders serial number extended capability virtio: hared dma-buf Fixes, cleanups all over the place. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (53 commits) libvhost-user: handle shared_object msg vhost-user: add shared_object msg hw/display: introduce virtio-dmabuf util/uuid: add a hash function virtio: remove unused next argument from virtqueue_split_read_next_desc() virtio: remove unnecessary thread fence while reading next descriptor virtio: use shadow_avail_idx while checking number of heads libvhost-user.c: add assertion to vu_message_read_default pcie_sriov: unregister_vfs(): fix error path hw/i386/pc: improve physical address space bound check for 32-bit x86 systems amd_iommu: Fix APIC address check vdpa net: follow VirtIO initialization properly at cvq isolation probing vdpa net: stop probing if cannot set features vdpa net: fix error message setting virtio status hw/pci-bridge/cxl-upstream: Add serial number extended capability support hw/cxl: Support 4 HDM decoders at all levels of topology hw/cxl: Fix and use same calculation for HDM decoder block size everywhere hw/cxl: Add utility functions decoder interleave ways and target count. hw/cxl: Push cxl_decoder_count_enc() and cxl_decode_ig() into .c vdpa net: zero vhost_vdpa iova_tree pointer at cleanup ... Conflicts: hw/core/machine.c Context conflict with commit 314e0a84cd5d ("hw/core: remove needless includes") because it removed an adjacent #include.
2023-10-04virtio-net: Expose MAX_VLANHawkins Jiawei
vhost-vdpa shadowed CVQ needs to know the maximum number of vlans supported by the virtio-net device, so QEMU can restore the VLAN state in a migration. Co-developed-by: Eugenio Pérez <eperezma@redhat.com> Signed-off-by: Eugenio Pérez <eperezma@redhat.com> Signed-off-by: Hawkins Jiawei <yin31149@gmail.com> Message-Id: <ca03403319c6405ea7c400836a572255bbc9ceba.1690106284.git.yin31149@gmail.com> Tested-by: Lei Yang <leiyang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-10-04virtio-net: do not reset vlan filtering at set_featuresHawkins Jiawei
This function is called after virtio_load, so all vlan configuration is lost in migration case. Just allow all the vlan-tagged packets if vlan is not configured, and trust device reset to clear all filtered vlans. Fixes: 0b1eaa8803 ("virtio-net: Do not filter VLANs without F_CTRL_VLAN") Signed-off-by: Eugenio Pérez <eperezma@redhat.com> Reviewed-by: Hawkins Jiawei <yin31149@gmail.com> Signed-off-by: Hawkins Jiawei <yin31149@gmail.com> Message-Id: <95af0d013281282f48ad3f47f6ad1ac4ca9e52eb.1690106284.git.yin31149@gmail.com> Tested-by: Lei Yang <leiyang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-09-29e1000: remove old compatibility codePaolo Bonzini
This code is not needed anymore in the supported machine types. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-09-20hw/net: spelling fixesMichael Tokarev
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2023-09-18hw/net/rocker: Avoid variable length arrayPeter Maydell
Replace an on-stack variable length array in of_dpa_ig() with a g_autofree heap allocation. The codebase has very few VLAs, and if we can get rid of them all we can make the compiler error on new additions. This is a defensive measure against security bugs where an on-stack dynamic allocation isn't correctly size-checked (e.g. CVE-2021-3527). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-09-18hw/net/fsl_etsec/rings.c: Avoid variable length arrayPeter Maydell
In fill_rx_bd() we create a variable length array of size etsec->rx_padding. In fact we know that this will never be larger than 64 bytes, because rx_padding is set in rx_init_frame() in a way that ensures it is only that large. Use a fixed sized array and assert that it is big enough. Since padd[] is now potentially rather larger than the actual padding required, adjust the memset() we do on it to match the size that we write with cpu_physical_memory_write(), rather than clearing the entire array. The codebase has very few VLAs, and if we can get rid of them all we can make the compiler error on new additions. This is a defensive measure against security bugs where an on-stack dynamic allocation isn't correctly size-checked (e.g. CVE-2021-3527). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-09-18e1000e: rename e1000e_ba_state and e1000e_write_hdr_to_rx_buffersTomasz Dzieciol
Rename e1000e_ba_state according and e1000e_write_hdr_to_rx_buffers for consistency with IGB. Signed-off-by: Tomasz Dzieciol <t.dzieciol@partner.samsung.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-09-18igb: packet-split descriptors supportTomasz Dzieciol
Packet-split descriptors are used by Linux VF driver for MTU values from 2048 Signed-off-by: Tomasz Dzieciol <t.dzieciol@partner.samsung.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-09-18igb: add IPv6 extended headers traffic detectionTomasz Dzieciol
Signed-off-by: Tomasz Dzieciol <t.dzieciol@partner.samsung.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-09-18igb: RX payload guest writting refactoringTomasz Dzieciol
Refactoring is done in preparation for support of multiple advanced descriptors RX modes, especially packet-split modes. Signed-off-by: Tomasz Dzieciol <t.dzieciol@partner.samsung.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-09-18igb: RX descriptors guest writting refactoringTomasz Dzieciol
Refactoring is done in preparation for support of multiple advanced descriptors RX modes, especially packet-split modes. Signed-off-by: Tomasz Dzieciol <t.dzieciol@partner.samsung.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-09-18igb: rename E1000E_RingInfo_stTomasz Dzieciol
Rename E1000E_RingInfo_st and E1000E_RingInfo according to qemu typdefs guide. Signed-off-by: Tomasz Dzieciol <t.dzieciol@partner.samsung.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-09-18igb: remove TCP ACK detectionTomasz Dzieciol
TCP ACK detection is no longer present in igb. Signed-off-by: Tomasz Dzieciol <t.dzieciol@partner.samsung.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-09-18virtio-net: Add support for USO featuresYuri Benditovich
USO features of virtio-net device depend on kernel ability to support them, for backward compatibility by default the features are disabled on 8.0 and earlier. Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com> Signed-off-by: Andrew Melnychecnko <andrew@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-09-18virtio-net: Add USO flags to vhost support.Andrew Melnychenko
New features are subject to check with vhost-user and vdpa. Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com> Signed-off-by: Andrew Melnychenko <andrew@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-09-18tap: Add USO support to tap device.Andrew Melnychenko
Passing additional parameters (USOv4 and USOv6 offloads) when setting TAP offloads Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com> Signed-off-by: Andrew Melnychenko <andrew@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-09-08hw/net/vmxnet3: Fix guest-triggerable assert()Thomas Huth
The assert() that checks for valid MTU sizes can be triggered by the guest (e.g. with the reproducer code from the bug ticket https://gitlab.com/qemu-project/qemu/-/issues/517 ). Let's avoid this problem by simply logging the error and refusing to activate the device instead. Fixes: d05dcd94ae ("net: vmxnet3: validate configuration values during activate") Signed-off-by: Thomas Huth <thuth@redhat.com> Cc: qemu-stable@nongnu.org Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> [Mjt: change format specifier from %d to %u for uint32_t argument]
2023-08-31hw/net/i82596: Include missing 'exec/address-spaces.h' headerPhilippe Mathieu-Daudé
hw/net/i82596.c access the global 'address_space_memory' calling the ld/st_phys() API. address_space_memory is declared in "exec/address-spaces.h". Currently this header is indirectly pulled in via another header. Explicitly include it to avoid when refactoring unrelated headers: hw/net/i82596.c:91:23: error: use of undeclared identifier 'address_space_memory'; did you mean 'address_space_destroy'? return ldub_phys(&address_space_memory, addr); ^~~~~~~~~~~~~~~~~~~~ address_space_destroy Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230619074153.44268-2-philmd@linaro.org>
2023-07-14kconfig: Add PCIe devices to s390x machinesCédric Le Goater
It is useful to extend the number of available PCIe devices to KVM guests for passthrough scenarios and also to expose these models to a different (big endian) architecture. Introduce a new config PCIE_DEVICES to select models, Intel Ethernet adapters and one USB controller. These devices all support MSI-X which is a requirement on s390x as legacy INTx are not supported. Cc: Matthew Rosato <mjrosato@linux.ibm.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Thomas Huth <thuth@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com> Message-ID: <20230712080146.839113-1-clg@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-07-10pcie: Use common ARI next function numberAkihiko Odaki
Currently the only implementers of ARI is SR-IOV devices, and they behave similar. Share the ARI next function number. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Ani Sinha <anisinha@redhat.com> Message-Id: <20230710153838.33917-2-akihiko.odaki@daynix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-07-10hw/virtio: fix typo in VIRTIO_CONFIG_IRQ_IDX commentsAlex Bennée
Fixes: 544f0278af (virtio: introduce macro VIRTIO_CONFIG_IRQ_IDX) Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230710153522.3469097-4-alex.bennee@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-07-10virtio-net: pass Device-TLB enable/disable events to vhostViktor Prutyanov
If vhost is enabled for virtio-net, Device-TLB enable/disable events must be passed to vhost for proper IOMMU unmap flag selection. Signed-off-by: Viktor Prutyanov <viktor@daynix.com> Acked-by: Jason Wang <jasowang@redhat.com> Message-Id: <20230626091258.24453-3-viktor@daynix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-07-07Merge tag 'pull-ppc-20230707-1' of https://gitlab.com/danielhb/qemu into stagingRichard Henderson
ppc patch queue for 2023-07-07: In this last queue for 8.1 we have a lot of fixes and improvements all around: SMT support for powerNV, XIVE fixes, PPC440 cleanups, exception handling cleanups and kvm_pph.h cleanups just to name a few. Thanks everyone in the qemu-ppc community for all the contributions for the next QEMU 8.1 release. # -----BEGIN PGP SIGNATURE----- # # iIwEABYKADQWIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCZKgihBYcZGFuaWVsaGI0 # MTNAZ21haWwuY29tAAoJEDzZypbeAzFksr0A/jrvSDSDxB5mR7bo0dNGndLXcdTo # ZGr6k6pcMpr7RDOAAQDVeaw7f8djQ4Aaelk6v1wPs5bYfNY2ElF4NsqHJFX2Cg== # =8lDs # -----END PGP SIGNATURE----- # gpg: Signature made Fri 07 Jul 2023 03:34:44 PM BST # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: issuer "danielhb413@gmail.com" # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20230707-1' of https://gitlab.com/danielhb/qemu: (59 commits) ppc/pnv: Add QME region for P10 target/ppc: Remove pointless checks of CONFIG_USER_ONLY in 'kvm_ppc.h' target/ppc: Restrict 'kvm_ppc.h' to sysemu in cpu_init.c target/ppc: Define TYPE_HOST_POWERPC_CPU in cpu-qom.h target/ppc: Move CPU QOM definitions to cpu-qom.h target/ppc: Reorder #ifdef'ry in kvm_ppc.h target/ppc: Have 'kvm_ppc.h' include 'sysemu/kvm.h' target/ppc: Machine check on invalid real address access on POWER9/10 tests/qtest: Add xscom tests for powernv10 machine ppc/pnv: Set P10 core xscom region size to match hardware ppc/pnv: Log all unimp warnings with similar message ppc440_pcix: Rename QOM type define abd move it to common header ppc4xx_pci: Add define for ppc4xx-host-bridge type name ppc4xx_pci: Rename QOM type name define ppc440_pcix: Stop using system io region for PCI bus ppc440_pcix: Don't use iomem for regs ppc/sam460ex: Remove address_space_mem local variable ppc440: Remove ppc460ex_pcie_init legacy init function ppc440: Add busnum property to PCIe controller model ppc440: Stop using system io region for PCIe buses ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-07igb: Remove obsolete workaround for WindowsAkihiko Odaki
I confirmed it works with Windows even without this workaround. It is likely to be a mistake so remove it. Fixes: 3a977deebe ("Intrdocue igb device emulation") Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-07-07e1000e: Add ICR clearing by corresponding IMS bitAkihiko Odaki
The datasheet does not say what happens when interrupt was asserted (ICR.INT_ASSERT=1) and auto mask is *not* active. However, section of 13.3.27 the PCIe* GbE Controllers Open Source Software Developer’s Manual, which were written for older devices, namely 631xESB/632xESB, 82563EB/82564EB, 82571EB/82572EI & 82573E/82573V/82573L, does say: > If IMS = 0b, then the ICR register is always clear-on-read. If IMS is > not 0b, but some ICR bit is set where the corresponding IMS bit is not > set, then a read does not clear the ICR register. For example, if > IMS = 10101010b and ICR = 01010101b, then a read to the ICR register > does not clear it. If IMS = 10101010b and ICR = 0101011b, then a read > to the ICR register clears it entirely (ICR.INT_ASSERTED = 1b). Linux does no longer activate auto mask since commit 0a8047ac68e50e4ccbadcfc6b6b070805b976885 and the real hardware clears ICR even in such a case so we also should do so. Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1707441 Signed-off-by: Andrew Melnychenko <andrew@daynix.com> Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-07-07hw/net: ftgmac100: Drop the small packet check in the receive pathBin Meng
Now that we have implemented unified short frames padding in the QEMU networking codes, the small packet check logic in the receive path is no longer needed. Suggested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Bin Meng <bmeng@tinylab.org> Signed-off-by: Jason Wang <jasowang@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-19 14:35:12 +0000