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2010-09-18Introduce range.hBlue Swirl
Extract range functions from pci.h. These will be used by later patches by non-PCI devices. Adjust current users. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-14Remove unused DEBUG defines from hw/msix.cJes Sorensen
Remove unused DEBUG defines from hw/msix.c to avoid having anything define the word DEBUG without any additions such as MSIX_DEBUG. Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-05-31msix: remove duplicated defines.Isaku Yamahata
remove defines which are already defined in pci_regs.h Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2009-12-23msix: use range helper function.Isaku Yamahata
use range helper function in msix_write_config(). Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2009-12-07msix: function mask supportMichael S. Tsirkin
Function mask is a mandatory feature in MSIX spec so not implementing it is a spec violation. Implement. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2009-12-07msix: macro rename for function mask supportMichael S. Tsirkin
rename ENABLE_OFFSET -> CONTROL_OFFSET, since same byte includes function mask. This is in preparation for function mask support. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2009-12-01msix: clear pending bit of an unused vectorMichael S. Tsirkin
PCI spec states: if a masked vector has its Pending bit set, and the associated underlying interrupt events are somehow satisfied (usually by software though the exact manner is function-specific), the function must clear the Pending bit, to avoid sending a spurious interrupt message later when software unmasks the vector. In our case this happens if vector becomes unused. Clear pending bit in this case. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2009-12-01msix: fix reset value for enable bitMichael S. Tsirkin
On reset, we currently clear all bits in msix control register *except* enable bit. This is wrong: the spec says we should clear writeable bits: function mask and enable bit. Correct this. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2009-12-01msix: fix mask bit state after resetMichael S. Tsirkin
PCI spec states that mask bit must be 1 after reset. Make it so. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2009-12-01msix: add helper to unuse all msix entriesMichael S. Tsirkin
will be used by virtio on soft reset Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2009-11-09pci: introduce pcibus_t to represent pci bus address/size instead of uint32_tIsaku Yamahata
This patch is preliminary for 64 bit BAR support. Introduce dedicated type, pcibus_t, to represent pci bus address/size instead of uint32_t. Later this type will be changed to uint64_t. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-30qemu/msix: fix table access issuesMichael S. Tsirkin
Fixes a couple of issues with msix table access: - With misbehaving guests, misaligned 4 byte access could overflow msix table and cause qemu to segfault. Since PCI spec requires host to only issue dword-aligned accesses, as a fix, it's enough to mask the address low bits. - Tables use pci format, not native format, and so we must use pci_[sg]et_long on read/write. Reported-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05qemu: clean up target page usage in msixMichael S. Tsirkin
Since cpu_register_phys_memory does not require size to be a multiple of target page size, simply make msix page size 0x1000. Do this in msix, reverting part of 5e520a7d500ec2569d22d80f9ef4272a34cb3c80, as we no longer have to pass target page around. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01Revert "Get rid of _t suffix"Anthony Liguori
In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01Get rid of _t suffixmalc
Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
2009-09-20Compile msix only onceBlue Swirl
Get page size in device init. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-25Make CPURead/WriteFunc structure 'const'Blue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-27qemu: msix nit: clear msix_entries_nr on errorMichael S. Tsirkin
I don't think it's critical to do this, but it's best to keep uninit and error recovery consistent. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-10qemu/msi: missing bracesMichael S. Tsirkin
MSIX present bit is tested incorrectly, and only happens to work because the bit we are testing is 0x1. Add braces to fix this. Reported-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-10qemu/msi: clean used vectors state on loadMichael S. Tsirkin
Clean up msix vector usage state on load. Since guest might have control over it through the device, the device will have to load this state from file. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-09fix segfault in msix_saveMichael S. Tsirkin
This fixes segfault reported by Kevin Wolf, and simplifies the code in msix_save. Reported-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-05Fix Sparse warningBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-24qemu/pci: MSI-X support functionsMichael S. Tsirkin
Add functions implementing MSI-X support. First user will be virtio-pci. Note that platform must set a flag to declare MSI supported: this is a safety measure to avoid breaking platforms which should support MSI-X but currently lack this in the interrupt controller emulation. For PC this will be set by APIC. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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