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2023-08-22kvm: Introduce kvm_arch_get_default_type hookAkihiko Odaki
kvm_arch_get_default_type() returns the default KVM type. This hook is particularly useful to derive a KVM type that is valid for "none" machine model, which is used by libvirt to probe the availability of KVM. For MIPS, the existing mips_kvm_type() is reused. This function ensures the availability of VZ which is mandatory to use KVM on the current QEMU. Cc: qemu-stable@nongnu.org Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-id: 20230727073134.134102-2-akihiko.odaki@daynix.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: added doc comment for new function] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-25hw/mips: Improve the default USB settings in the loongson3-virt machineThomas Huth
It's possible to compile QEMU without the USB devices (e.g. when using "--without-default-devices" as option for the "configure" script). To be still able to run the loongson3-virt machine in default mode with such a QEMU binary, we have to check here for the availability of the OHCI controller first before instantiating the USB devices. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230714104903.284845-1-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-11Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Richard Henderson
into staging pc,pci,virtio: cleanups, fixes, features vhost-user-gpu: edid vhost-user-scmi device vhost-vdpa: _F_CTRL_RX and _F_CTRL_RX_EXTRA support for svq cleanups, fixes all over the place. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmSsjYMPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRp2vYH/20u6TAMssE/UAJoUU0ypbJkbHjDqiqDeuZN # qDYazLUWIJTUbDnSfXAiRcdJuukEpEFcoHa9O6vgFE/SNod51IrvsJR9CbZxNmk6 # D+Px9dkMckDE/yb8f6hhcHsi7/1v04I0oSXmJTVYxWSKQhD4Km6x8Larqsh0u4yd # n6laZ+VK5H8sk6QvI5vMz+lYavACQVryiWV/GAigP21B0eQK79I5/N6y0q8/axD5 # cpeTzUF+m33SfLfyd7PPmibCQFYrHDwosynSnr3qnKusPRJt2FzWkzOiZgbtgE2L # UQ/S4sYTBy8dZJMc0wTywbs1bSwzNrkQ+uS0v74z9wCUYTgvQTA= # =RsOh # -----END PGP SIGNATURE----- # gpg: Signature made Tue 11 Jul 2023 12:00:19 AM BST # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [undefined] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (66 commits) vdpa: Allow VIRTIO_NET_F_CTRL_RX_EXTRA in SVQ vdpa: Restore packet receive filtering state relative with _F_CTRL_RX_EXTRA feature vdpa: Allow VIRTIO_NET_F_CTRL_RX in SVQ vdpa: Avoid forwarding large CVQ command failures vdpa: Accessing CVQ header through its structure vhost: Fix false positive out-of-bounds vdpa: Restore packet receive filtering state relative with _F_CTRL_RX feature vdpa: Restore MAC address filtering state vdpa: Use iovec for vhost_vdpa_net_load_cmd() pcie: Specify 0 for ARI next function numbers pcie: Use common ARI next function number include/hw/virtio: document some more usage of notifiers include/hw/virtio: add kerneldoc for virtio_init include/hw/virtio: document virtio_notify_config hw/virtio: fix typo in VIRTIO_CONFIG_IRQ_IDX comments include/hw: document the device_class_set_parent_* fns include: attempt to document device_class_set_props vdpa: Fix possible use-after-free for VirtQueueElement pcie: Add hotplug detect state register to cmask virtio-iommu: Rework the traces in virtio_iommu_set_page_size_mask() ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-10hw/mips/loongson3_virt: Relax CPU restrictions for TCGJiaxun Yang
After implemented CPUCFG and CSR, we are now able to boot Linux kernel with Loongson-3A4000 CPU, so there is no point to restrict CPU type to 3A1000 only, instead we just check for presence of INSN_LOONGSON3A. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20230521214832.20145-3-jiaxun.yang@flygoat.com> [JY: Check for cpu_type_supports_isa(INSN_LOONGSON3A)] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10hw/pci/pci: Remove multifunction parameter from ↵Bernhard Beschow
pci_create_simple_multifunction() There is also pci_create_simple() which creates non-multifunction PCI devices. Accordingly the parameter is always set to true when a multi function PCI device is to be created. The reason for the parameter's existence seems to be that it is used in the internal PCI code as well which is the only location where it gets set to false. This one usage can be replaced by trivial code. Remove this redundant, error-prone parameter. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20230304114043.121024-5-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-07-08hw: Simplify calls to pci_nic_init_nofail()Thomas Huth
pci_nic_init_nofail() calls qemu_find_nic_model(), and this function sets nd->model = g_strdup(default_model) if it has not been initialized yet. So we don't have to set nd->model to the default_nic in the calling sites. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2023-06-05hw/mips/malta: Fix the malta machine on big endian hostsThomas Huth
Booting a Linux kernel with the malta machine is currently broken on big endian hosts. The cpu_to_gt32 macro wants to byteswap a value for little endian targets only, but uses the wrong way to do this: cpu_to_[lb]e32 works the other way round on big endian hosts! Fix it by using the same ways on both, big and little endian hosts. Fixes: 0c8427baf0 ("hw/mips/malta: Use bootloader helper to set BAR registers") Cc: qemu-stable@nongnu.org Message-Id: <20230330152613.232082-1-thuth@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-05-26hw/mips: Use MachineClass->default_nic in the virt machinePhilippe Mathieu-Daudé
Mark the default NIC via the new MachineClass->default_nic setting so that the machine-defaults code in vl.c can decide whether the default NIC is usable or not (for example when compiling with the "--without-default-devices" configure switch). Inspired-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230524122559.28863-1-philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-05-12hw/mips/malta: Fix minor dead code issuePeter Maydell
Coverity points out (in CID 1508390) that write_bootloader has some dead code, where we assign to 'p' and then in the following line assign to it again. This happened as a result of the refactoring in commit cd5066f8618b. Fix the dead code by removing the 'void *v' variable entirely and instead adding a cast when calling bl_setup_gt64120_jump_kernel(), as we do at its other callsite in write_bootloader_nanomips(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-03-08hw/mips/itu: Pass SAAR using QOM link propertyPhilippe Mathieu-Daudé
QOM objects shouldn't access each other internals fields except using the QOM API. mips_cps_realize() instantiates a TYPE_MIPS_ITU object, and directly sets the 'saar' pointer: if (saar_present) { s->itu.saar = &env->CP0_SAAR; } In order to avoid that, pass the MIPS_CPU object via a QOM link property, and set the 'saar' pointer in mips_itu_realize(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20230203113650.78146-10-philmd@linaro.org>
2023-03-08hw/mips: Declare all length properties as unsignedPhilippe Mathieu-Daudé
Some length properties are signed, other unsigned: hw/mips/cps.c:183: DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1), hw/mips/cps.c:184: DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256), hw/misc/mips_cmgcr.c:215: DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1), hw/misc/mips_cpc.c:167: DEFINE_PROP_UINT32("num-vp", MIPSCPCState, num_vp, 0x1), hw/misc/mips_itu.c:552: DEFINE_PROP_INT32("num-fifo", MIPSITUState, num_fifo, hw/misc/mips_itu.c:554: DEFINE_PROP_INT32("num-semaphores", MIPSITUState, Since negative values are not used (the minimum is '0'), unify by declaring all properties as unsigned. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230203113650.78146-9-philmd@linaro.org>
2023-02-27hw/isa: Rename isa_bus_irqs() -> isa_bus_register_input_irqs()Philippe Mathieu-Daudé
isa_bus_irqs() register an array of input IRQs on the ISA bus. Rename it as isa_bus_register_input_irqs(). Mechanical change using: $ sed -i -e 's/isa_bus_irqs/isa_bus_register_input_irqs/g' \ $(git grep -wl isa_bus_irqs) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230210163744.32182-10-philmd@linaro.org>
2023-01-13hw/mips/boston: Rename MachineState 'mc' pointer to 'ms'Daniel Henrique Barboza
Follow the QEMU convention of naming MachineState pointers as 'ms' by renaming the instance in create_fdt() where we're calling it 'mc'. Cc: Paul Burton <paulburton@kernel.org> Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20230111172133.334735-1-dbarboza@ventanamicro.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/mips/Kconfig: Track Malta's PIIX dependencies via KconfigBernhard Beschow
Tracking dependencies via Kconfig seems much cleaner. Note that PIIX4 already depends on ACPI_PIIX4. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20230109172347.1830-8-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specificBernhard Beschow
pci_map_irq_fn's in general seem to be board-specific, and PIIX4's pci_slot_get_pirq() in particular seems very Malta-specific. So move the latter to malta.c to 1/ keep the board logic in one place and 2/ avoid PIIX4 to make assumptions about its board. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230109172347.1830-7-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13mips: Remove support for trap and emulate KVMPaolo Bonzini
This support was limited to the Malta board, drop it. I do not have a machine that can run VZ KVM, so I am assuming that it works for -M malta as well. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221221091718.71844-1-philmd@linaro.org>
2023-01-13hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloaderPhilippe Mathieu-Daudé
Linux kernel expects the northbridge & southbridge chipsets configured by the BIOS firmware. We emulate that by writing a tiny bootloader code in write_bootloader(). Upon introduction in commit 5c2b87e34d ("PIIX4 support"), the PIIX4 configuration space included values specific to the Malta board. Set the Malta-specific IRQ routing values in the embedded bootloader, so the next commit can remove the Malta specific bits from the PIIX4 PCI-ISA bridge and make it generic (matching the real hardware). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20221027204720.33611-3-philmd@linaro.org>
2023-01-13hw/mips/malta: Introduce PIIX4_PCI_DEVFN definitionPhilippe Mathieu-Daudé
The PIIX4 PCI-ISA bridge function is always located at 10:0. Since we want to re-use its address, add the PIIX4_PCI_DEVFN definition. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20221027204720.33611-2-philmd@linaro.org>
2023-01-13hw/mips/malta: Merge common BL code as bl_setup_gt64120_jump_kernel()Philippe Mathieu-Daudé
Merge common code shared between write_bootloader() and write_bootloader_nanomips() into bl_setup_gt64120_jump_kernel(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221211204533.85359-12-philmd@linaro.org>
2023-01-13hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (5/5)Philippe Mathieu-Daudé
Part 5/5: Convert jumping to kernel Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221211204533.85359-11-philmd@linaro.org>
2023-01-13hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (4/5)Philippe Mathieu-Daudé
Part 4/5: Convert GT64120 ISD base address setup Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221211204533.85359-10-philmd@linaro.org>
2023-01-13hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (3/5)Philippe Mathieu-Daudé
Part 3/5: Convert PCI0 I/O BAR setup Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221211204533.85359-9-philmd@linaro.org>
2023-01-13hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (2/5)Philippe Mathieu-Daudé
Part 2/5: Convert PCI0 MEM0 BAR setup Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221211204533.85359-8-philmd@linaro.org>
2023-01-13hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (1/5)Philippe Mathieu-Daudé
Similarly to how commit 0c8427baf0 ("hw/mips/malta: Use bootloader helper to set BAR registers") converted write_bootloader(), convert the equivalent write_bootloader_nanomips(), allowing us to modify the bootloader code more easily in the future. Part 1/5: Convert PCI0 MEM1 BAR setup Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221211204533.85359-7-philmd@linaro.org>
2023-01-13hw/mips/bootloader: Implement nanoMIPS JALRc opcode generatorPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221211204533.85359-6-philmd@linaro.org>
2023-01-13hw/mips/bootloader: Implement nanoMIPS LI (LUI+ORI) opcode generatorPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221211204533.85359-5-philmd@linaro.org>
2023-01-13hw/mips/bootloader: Implement nanoMIPS SW opcode generatorPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221211204533.85359-4-philmd@linaro.org>
2023-01-13hw/mips/bootloader: Implement nanoMIPS NOP opcode generatorPhilippe Mathieu-Daudé
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221211204533.85359-3-philmd@linaro.org>
2023-01-13hw/mips/bootloader: Handle buffers as opaque arraysPhilippe Mathieu-Daudé
It is irrelevant to the API what the buffers to fill are made of. In particular, some MIPS ISA have 16-bit wide instructions. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221211204533.85359-2-philmd@linaro.org>
2023-01-13hw/mips/gt64xxx_pci: Move it to hw/pci-host/Philippe Mathieu-Daudé
The GT-64120 is a north-bridge, and it is not MIPS specific. Move it with the other north-bridge devices. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20221209151533.69516-8-philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-13hw/mips/meson: Make gt64xxx_pci.c endian-agnosticPhilippe Mathieu-Daudé
The single machine using this device explicitly sets its endianness. We don't need to set a default. This allow us to remove the target specificity from the build system. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20221209151533.69516-7-philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-13hw/mips/malta: Explicit GT64120 endianness upon device creationPhilippe Mathieu-Daudé
Propagate the controller endianess from the machine, setting the "cpu-little-endian" property. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221209151533.69516-6-philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-13hw/mips/gt64xxx_pci: Add a 'cpu-little-endian' qdev propertyPhilippe Mathieu-Daudé
This device does not have to be TARGET-dependent. Add a 'cpu_big_endian' property which sets the byte-swapping options if required. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20221220113436.14299-5-philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-13hw/mips/gt64xxx_pci: Manage endian bits with the RegisterFields APIPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221220113436.14299-4-philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-13hw/mips/gt64xxx_pci: Let the GT64120 manage the lower 512MiB holePhilippe Mathieu-Daudé
Per the comment in the Malta board, the [0x0000.0000-0x2000.0000] range is decoded by the GT64120, so move the "empty_slot" there. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20221209151533.69516-3-philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-13hw/mips/Kconfig: Introduce CONFIG_GT64120 to select gt64xxx_pci.cPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20221209151533.69516-2-philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-13hw/mips/gt64xxx_pci: Endian-swap using PCI_HOST_BRIDGE MemoryRegionOpsPhilippe Mathieu-Daudé
GT64120's PCI endianness swapping works on little-endian hosts, but doesn't on big-endian ones. Instead of complicating how CFGADDR/CFGDATA registers deal with endianness, use the existing MemoryRegionOps from hw/pci/pci_host.c. Doing so also reduce the access to internal PCI_HOST_BRIDGE fields. Map the PCI_HOST_BRIDGE MemoryRegionOps into the corresponding CFGADDR/CFGDATA regions in the ISD MMIO and remove the unused code in the current ISD read/write handlers. Update the mapping when PCI0_CMD register is accessed (in case the endianness is changed). This allows using the GT64120 on a big-endian host (and boot the MIPS Malta machine in little-endian). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230104133935.4639-6-philmd@linaro.org>
2023-01-13hw/mips/gt64xxx_pci: Accumulate address space changesPhilippe Mathieu-Daudé
Single registers access in ISD can produce multiple changes in the address spaces. To reduce computational effort, accumulate these as a single memory transaction. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230104133935.4639-5-philmd@linaro.org>
2023-01-13hw/mips/malta: Trace FPGA LEDs/ASCII display updatesPhilippe Mathieu-Daudé
The FPGA LEDs/ASCII display is mostly used by the bootloader to show very low-level debug info. QEMU connects its output to a character device backend, which is not very practical to correlate with ASM instruction executed, interrupts or MMIO accesses. Also, the display discard the previous states. To ease bootloader debugging experience, add a pair of trace events. Such events can be analyzed over time or diff-ed between different runs. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230104133935.4639-4-philmd@linaro.org>
2023-01-13hw/mips/malta: Split FPGA LEDs/ASCII display updatesPhilippe Mathieu-Daudé
No need to refresh the ASCII bar when a LED is toggled (and vice versa). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230104133935.4639-3-philmd@linaro.org>
2023-01-08include/hw/pci: Split pci_device.h off pci.hMarkus Armbruster
PCIDeviceClass and PCIDevice are defined in pci.h. Many users of the header don't actually need them. Similar structs live in their own headers: PCIBusClass and PCIBus in pci_bus.h, PCIBridge in pci_bridge.h, PCIHostBridgeClass and PCIHostState in pci_host.h, PCIExpressHost in pcie_host.h, and PCIERootPortClass, PCIEPort, and PCIESlot in pcie_port.h. Move PCIDeviceClass and PCIDeviceClass to new pci_device.h, along with the code that needs them. Adjust include directives. This also enables the next commit. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20221222100330.380143-6-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-01-04hw/mips: Use QEMU_IOTHREAD_LOCK_GUARD in cpu_mips_irq_requestRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-10-31hw/mips/malta: Use bootloader helper to set BAR registersJiaxun Yang
Translate embedded assembly into IO writes which is more readable. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20210127065424.114125-4-jiaxun.yang@flygoat.com> [PMD: Explode addresses/values to ease review/maintainance] Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221026191821.28167-4-philmd@linaro.org>
2022-10-31hw/mips: Use bl_gen_kernel_jump to generate bootloadersJiaxun Yang
Replace embedded binary with generated code. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20210127065424.114125-3-jiaxun.yang@flygoat.com> [PMD: Pass semihosting_get_argc() to bl_gen_jump_kernel()] Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221026191821.28167-3-philmd@linaro.org>
2022-10-31hw/mips/bootloader: Allow bl_gen_jump_kernel to optionally set registerPhilippe Mathieu-Daudé
When one of the $sp/$a[0..3] register is already set, we might want bl_gen_jump_kernel() to NOT set it again. Pass a boolean argument for each register, to allow to optionally set them. Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221026191821.28167-2-philmd@linaro.org>
2022-10-31hw/mips/boston: Don't set link_up for xilinx-pcieJiaxun Yang
PCIe port 0 and 1 had link_up set as false previously, that makes those two ports effectively useless. It can be annoying for users to find that the device they plug on those buses won't work at all. As link_up is true by default, just don't set it again in boston platform code. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20221024143540.97545-1-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-10-31hw/isa/piix4: Move pci_ide_create_devs() call to board codeBernhard Beschow
For the VIA south bridges there was a comment to have the call in board code. Move it there for PIIX4 as well for consistency. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20221022150508.26830-29-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-10-31hw/mips/malta: Reuse dev variableBernhard Beschow
While at it, move the assignments closer to where they are used. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221022150508.26830-26-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-10-31hw: Remove unused MAX_IDE_BUS defineBALATON Zoltan
Several machines have an unused MAX_IDE_BUS define. Remove it from these machines that don't need it. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220917115136.A32EF746E06@zero.eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-10-31hw/isa/vt82c686: Create rtc-time alias in boards insteadBernhard Beschow
According to good QOM practice, an object should only deal with objects of its own sub tree. Having devices create an alias on the machine object doesn't respect this good practice. To resolve this, create the alias in the machine's code. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220901114127.53914-14-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
generated by cgit v1.2.3 (git 2.26.2) at 2024-11-26 20:37:23 +0000