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2021-01-04hw/mips/fuloong2e: Replace faulty documentation linksJiaxun Yang
Websites are downing, but GitHub may last forever. Loongson even doesn't recogonize 2E as their products nowadays.. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Huacai Chen <chenhuacai@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201224031750.52146-3-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04hw/mips/fuloong2e: Remove define DEBUG_FULOONG2E_INITJiaxun Yang
Seems useless.... Fixes: 051c190bce5 ("MIPS: Initial support of fulong mini pc (machine construction)") Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Huacai Chen <chenhuacai@kernel.org> Message-Id: <20201224031750.52146-2-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04hw/mips: Use address translation helper to handle ENVP_ADDRJiaxun Yang
It will signed extend vaddr properly. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201215064200.28751-4-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04hw/mips/malta: Use address translation helper to calculate bootloader_run_addrJiaxun Yang
So it will sign extend adresses properly. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201215064200.28751-3-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04hw/mips: Make bootloader addresses unsignedJiaxun Yang
Address should be unsigned anyway, otherwise it may carry calculations wrongly. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201215064200.28751-2-jiaxun.yang@flygoat.com> [PMD: Fixed typo and convert hw/mips/mipssim.c too] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04hw/mips: Add Loongson-3 machine supportHuacai Chen
Add Loongson-3 based machine support, it use liointc as the interrupt controler and use GPEX as the pci controller. Currently it can work with both TCG and KVM. As the machine model is not based on any exiting physical hardware, the name of the machine is "loongson3-virt". It may be superseded in future by a real machine model. If this happens, then a regular deprecation procedure shall occur for "loongson3-virt" machine. We now already have a full functional Linux kernel (based on Linux-5.4.x LTS) here: https://github.com/chenhuacai/linux Of course the upstream kernel is also usable (the kvm host side and guest side have both been upstream in Linux-5.9): https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git How to use QEMU/Loongson-3? 1, Download kernel source from the above URL; 2, Build a kernel with arch/mips/configs/loongson3_defconfig; 3, Boot a Loongson-3A4000 host with this kernel (for KVM mode); 4, Build QEMU-master with this patchset; 5, modprobe kvm (only necessary for KVM mode); 6, Use QEMU with TCG: qemu-system-mips64el -M loongson3-virt,accel=tcg -cpu Loongson-3A1000 -kernel <path_to_kernel> -append ... Use QEMU with KVM: qemu-system-mips64el -M loongson3-virt,accel=kvm -cpu Loongson-3A4000 -kernel <path_to_kernel> -append ... The "-cpu" parameter is optional here and QEMU will use the correct type for TCG/KVM automatically. Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@kernel.org> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201221110538.3186646-5-chenhuacai@kernel.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: Set TYPE_LOONGSON_MACHINE instance_size in TypeInfo, select FW_CFG_MIPS in Kconfig] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04hw/mips: Add Loongson-3 boot parameter helpersHuacai Chen
Preparing to add Loongson-3 machine support, add Loongson-3's LEFI (a UEFI-like interface for BIOS-Kernel boot parameters) helpers first. Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@kernel.org> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201221110538.3186646-4-chenhuacai@kernel.org> [PMD: Fixed typo] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04hw/mips: Implement fw_cfg_arch_key_name()Huacai Chen
Implement fw_cfg_arch_key_name(), which returns the name of a mips-specific key. Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@kernel.org> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1600742967-12933-7-git-send-email-chenhc@lemote.com> [PMD: Add FW_CFG_MIPS Kconfig selector] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04vt82c686: Remove legacy vt82c686b_pm_init() functionBALATON Zoltan
Remove legacy vt82c686b_pm_init() function and also rename VT82C686B_PM type name to match other device names. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <a70982b32f11222d335385b90749abb6cf2e2cce.1609584216.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04vt82c686: Remove legacy vt82c686b_isa_init() functionBALATON Zoltan
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <58d7585f979f154b1f1e69fdc026eed6dbc7996f.1609584216.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04vt82c686: Remove vt82c686b_[am]c97_init() functionsBALATON Zoltan
These are legacy init functions that are just equivalent to directly calling pci_create_simple so do that instead. Also rename objects to lower case via-ac97 and via-mc97 matching naming of other devices. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1c4373c8aeb6c4fb2a8df2c864b0e91a977a3d7b.1609584216.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-04hw: Use the PCI_SLOT() macro from 'hw/pci/pci.h'Philippe Mathieu-Daudé
We already have a generic PCI_SLOT() macro in "hw/pci/pci.h" to extract the PCI slot identifier, use it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Paul Durrant <paul@xen.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20201012124506.3406909-5-philmd@redhat.com>
2020-12-13hw/mips/malta: Rewrite CP0_MVPConf0 access using deposit()Philippe Mathieu-Daudé
PTC field has 8 bits, PVPE has 4. We plan to use the "hw/registerfields.h" API with MIPS CPU definitions (target/mips/cpu.h). Meanwhile we use magic 8 and 4. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201204222622.2743175-6-f4bug@amsat.org>
2020-12-13hw/mips/malta: Do not initialize MT registers if MT ASE absentPhilippe Mathieu-Daudé
Do not initialize MT-related config register if the MT ASE is not present. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201204222622.2743175-5-f4bug@amsat.org>
2020-12-13target/mips: Introduce ase_mt_available() helperPhilippe Mathieu-Daudé
Instead of accessing CP0_Config3 directly and checking the 'Multi-Threading Present' bit, introduce an helper to simplify code review. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201204222622.2743175-3-f4bug@amsat.org>
2020-12-13hw/mips: Move address translation helpers to target/mips/Philippe Mathieu-Daudé
Address translation is an architectural thing (not hardware related). Move the helpers from hw/ to target/. As physical address and KVM are specific to system mode emulation, restrict this file to softmmu, so it doesn't get compiled for user-mode emulation. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-2-f4bug@amsat.org>
2020-12-13target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT()Philippe Mathieu-Daudé
As cpu_supports_isa() / cpu_supports_cps_smp() take a 'cpu_type' name argument, rename them cpu_type_supports_FEAT(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201207215257.4004222-2-f4bug@amsat.org>
2020-12-10vl: extract softmmu/datadir.cPaolo Bonzini
Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-12-10mips: do not use ram_size globalPaolo Bonzini
Use the machine properties or loader parameters instead. Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-12-10mips: remove bios_namePaolo Bonzini
Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20201026143028.3034018-9-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-11-09hw/mips/boston: Fix memory leak in boston_fdt_filter() error-handling pathsPeter Maydell
Coverity points out that the error-handling paths in the boston_fdt_filter() function don't free the fdt that was allocated. Fix the leak by using g_autofree. Fixes: Coverity CID 1432275 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201106175823.1650-1-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-11-03hw/mips/boston: Fix Lesser GPL version numberChetan Pant
There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20201023122633.19466-1-chetan4windows@gmail.com> [PMD: Added hw/mips/ prefix in subject] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-11-03hw/mips: Fix Lesser GPL version numberChetan Pant
There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20201016143509.26692-1-chetan4windows@gmail.com> [PMD: Split hw/ vs target/] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-11-03hw/mips: Remove the 'r4k' machinePhilippe Mathieu-Daudé
We deprecated the support for the 'r4k' machine for the 5.0 release (commit d32dc61421), which means that our deprecation policy allows us to drop it in release 5.2. Remove the code. To repeat the rationale from the deprecation note: - this virtual machine has no specification - the Linux kernel dropped support for it 10 years ago Users are recommended to use the Malta board instead. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> ACKed-by: Peter Krempa <pkrempa@redhat.com> Message-Id: <20201102201311.2220005-1-f4bug@amsat.org>
2020-10-17hw/mips: Remove exit(1) in case of missing ROMPavel Dovgalyuk
This patch updates MIPS-based machines to allow starting them without ROM. In this case CPU starts to execute instructions from the empty memory, but QEMU allows introspecting the machine configuration. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <159531210571.24117.231100997794891819.stgit@pasha-ThinkPad-X280> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-10-17hw/mips: Rename TYPE_MIPS_BOSTON to TYPE_BOSTONEduardo Habkost
This will make the type name constant consistent with the name of the type checking macro. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200902224311.1321159-19-ehabkost@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-10-17hw/mips: Simplify code using ROUND_UP(INITRD_PAGE_SIZE)Philippe Mathieu-Daudé
Instead of using a INITRD_PAGE_MASK definition, use the simpler INITRD_PAGE_SIZE one which allows us to simplify the code by using directly the self-explicit ROUND_UP() macro. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200927163943.614604-3-f4bug@amsat.org>
2020-10-17hw/mips: Simplify loading 64-bit ELF kernelsPhilippe Mathieu-Daudé
Since 82790064116 ("Cast ELF datatypes properly to host 64bit types") we don't need to sign-extend the entry_point address. Remove this unnecessary code. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200927163943.614604-2-f4bug@amsat.org>
2020-10-17hw/mips/malta: Use clearer qdev stylePhilippe Mathieu-Daudé
In order to be consistent with the other code base uses, rewrite slightly how the MIPS_MALTA object is created. No logical change. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201012160503.3472140-3-f4bug@amsat.org>
2020-10-17hw/mips/malta: Move gt64120 related code togetherPhilippe Mathieu-Daudé
The 'empty_slot' region created is related to the gt64120. Move its creation close to the gt64120 instance creation. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201012160503.3472140-2-f4bug@amsat.org>
2020-10-17hw/mips/malta: Fix FPGA I/O region sizePhilippe Mathieu-Daudé
The FPGA present on the CoreCard has an I/O region 1MiB wide. Refs: - Atlas User’s Manual (Document Number: MD00005) - Malta User’s Manual (Document Number: MD00048) Fixes: ea85df72b60 ("mips_malta: convert to memory API") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200905213049.761949-1-f4bug@amsat.org>
2020-10-17hw/mips/cps: Do not allow use without input clockPhilippe Mathieu-Daudé
Now than all QOM users provides the input clock, do not allow using a CPS without input clock connected. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-21-f4bug@amsat.org>
2020-10-17hw/mips/malta: Set CPU frequency to 320 MHzPhilippe Mathieu-Daudé
The CoreLV card with ID 0x420's CPU clocked at 320 MHz. Create a 'cpuclk' output clock and connect it to the CPU input clock. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-20-f4bug@amsat.org>
2020-10-17hw/mips/boston: Set CPU frequency to 1 GHzPhilippe Mathieu-Daudé
The I6400 can run at 1 GHz or more. Create a 'cpuclk' output clock and connect it to the CPU input clock. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-19-f4bug@amsat.org>
2020-10-17hw/mips/cps: Expose input clock and connect it to CPU coresPhilippe Mathieu-Daudé
Expose a qdev input clock named 'clk-in', and connect it to each core to forward-propagate the clock. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-18-f4bug@amsat.org>
2020-10-17hw/mips/jazz: Correct CPU frequenciesPhilippe Mathieu-Daudé
The Magnum 4000PC CPU runs at 100 MHz, and the Acer PICA-61 CPU at ~134 MHz. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-17-f4bug@amsat.org>
2020-10-17hw/mips/mipssim: Correct CPU frequencyPhilippe Mathieu-Daudé
The MIPSsim machine CPU frequency is too fast running at 200 MHz, while it should be 12 MHz for the 24K and 6 MHz for the 5K core. Ref: Linux commit c78cbf49c4ed ("Support for MIPSsim, the cycle accurate MIPS simulator.") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-16-f4bug@amsat.org>
2020-10-17hw/mips/fuloong2e: Set CPU frequency to 533 MHzPhilippe Mathieu-Daudé
The CPU frequency is normally provided by the firmware in the "cpuclock" environment variable. The 2E board can handles up to 660MHz, but be conservative and take the same value used by the Linux kernel: 533 MHz. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201012095804.3335117-15-f4bug@amsat.org>
2020-10-17hw/mips/r4k: Explicit CPU frequency is 200 MHzPhilippe Mathieu-Daudé
Since its introduction in commit 6af0bf9c7c3, the 'r4k' machine runs at 200 MHz. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-14-f4bug@amsat.org>
2020-09-30hw/mips/mipssim: Use MMIO serial device on fake ISA I/OPhilippe Mathieu-Daudé
The 'mipssim' is not a real hardware, it is a simulator. There is an ISA MMIO space mapped at 0x1fd00000, however this is not a real ISA bus (no ISA IRQ). So can not use the TYPE_ISA_SERIAL device... Instead we have been using a plain MMIO device, but named it IO. TYPE_SERIAL_IO is a subset of TYPE_SERIAL_MM, using regshift=0 and endianness=DEVICE_LITTLE_ENDIAN. Directly use the TYPE_SERIAL_MM device, enforcing the regshift/endianness values. 'regshift' default is already '0'. 'endianness' is meaningless for 8-bit accesses. This change breaks migration back compatibility, but this is not an issue for the mipssim machine. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200907011538.818996-2-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-25load_elf: Remove unused address variables from callersBALATON Zoltan
Several callers of load_elf() pass pointers for lowaddr and highaddr parameters which are then not used for anything. This may stem from a misunderstanding that load_elf need a value here but in fact it can take NULL to ignore these values. Remove such unused variables and pass NULL instead from callers that don't need these. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Message-Id: <20200705174020.BDD0174633F@zero.eik.bme.hu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-18Use OBJECT_DECLARE_SIMPLE_TYPE when possibleEduardo Habkost
This converts existing DECLARE_INSTANCE_CHECKER usage to OBJECT_DECLARE_SIMPLE_TYPE when possible. $ ./scripts/codeconverter/converter.py -i \ --pattern=AddObjectDeclareSimpleType $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Paul Durrant <paul@xen.org> Message-Id: <20200916182519.415636-6-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-12Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier2/tags/trivial-branch-for-5.2-pull-request' into staging trivial patches pull request 20200911 # gpg: Signature made Fri 11 Sep 2020 20:32:27 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-for-5.2-pull-request: target/i386/kvm: Add missing fallthrough comment util/hexdump: Reorder qemu_hexdump() arguments util/hexdump: Convert to take a void pointer argument hw/arm/pxa2xx: Add missing fallthrough comment target/i386/kvm: Rename host_tsx_blacklisted() as host_tsx_broken() test-vmstate: remove unnecessary code in match_interval_mapping_node hw: hyperv: vmbus: Fix 32bit compilation kconfig: fix comment referring to old Makefiles meson.build: tweak sdl-image error message hw/net/e1000e: Remove duplicated write handler for FLSWDATA register hw/net/e1000e: Remove overwritten read handler for STATUS register Makefile: Skip the meson subdir in cscope/TAGS/ctags Makefile: Drop extra phony cscope hw/gpio/max7310: Replace disabled printf() by qemu_log_mask(UNIMP) hw/gpio/omap_gpio: Replace fprintf() by qemu_log_mask(GUEST_ERROR) hw/acpi/tco: Remove unused definitions hw/isa/isa-bus: Replace hw_error() by assert() hw/mips/fuloong2e: Convert pointless error message to an assert() Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # net/colo-compare.c
2020-09-11Merge remote-tracking branch ↵Peter Maydell
'remotes/ehabkost/tags/machine-next-pull-request' into staging QOM boilerplate cleanup Documentation build fix: * memory: Remove kernel-doc comment marker (Eduardo Habkost) QOM cleanups: * Rename QOM macros for consistency between TYPE_* and type checking constants (Eduardo Habkost) QOM new macros: * OBJECT_DECLARE_* and OBJECT_DEFINE_* macros (Daniel P. Berrangé) * DECLARE_*_CHECKER macros (Eduardo Habkost) Automated QOM boilerplate changes: * Automated changes to use DECLARE_*_CHECKER (Eduardo Habkost * Automated changes to use OBJECT_DECLARE* (Eduardo Habkost) # gpg: Signature made Thu 10 Sep 2020 19:17:49 BST # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/machine-next-pull-request: (33 commits) virtio-vga: Use typedef name for instance_size vhost-user-vga: Use typedef name for instance_size xilinx_axienet: Use typedef name for instance_size lpc_ich9: Use typedef name for instance_size omap_intc: Use typedef name for instance_size xilinx_axidma: Use typedef name for instance_size tusb6010: Rename TUSB to TUSB6010 pc87312: Rename TYPE_PC87312_SUPERIO to TYPE_PC87312 vfio: Rename PCI_VFIO to VFIO_PCI usb: Rename USB_SERIAL_DEV to USB_SERIAL sabre: Rename SABRE_DEVICE to SABRE rs6000_mc: Rename RS6000MC_DEVICE to RS6000MC filter-rewriter: Rename FILTER_COLO_REWRITER to FILTER_REWRITER esp: Rename ESP_STATE to ESP ahci: Rename ICH_AHCI to ICH9_AHCI vmgenid: Rename VMGENID_DEVICE to TYPE_VMGENID vfio: Rename VFIO_AP_DEVICE_TYPE to TYPE_VFIO_AP_DEVICE dev-smartcard-reader: Rename CCID_DEV_NAME to TYPE_USB_CCID_DEV ap-device: Rename AP_DEVICE_TYPE to TYPE_AP_DEVICE gpex: Fix type checking function name ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-09esp: Rename ESP_STATE to ESPEduardo Habkost
Make the type checking macro name consistent with the TYPE_* constant. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Hervé Poussineau <hpoussin@reactos.org> Message-Id: <20200902224311.1321159-40-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-09trace-events: Fix attribution of trace points to sourceMarkus Armbruster
Some trace points are attributed to the wrong source file. Happens when we neglect to update trace-events for code motion, or add events in the wrong place, or misspell the file name. Clean up with help of scripts/cleanup-trace-events.pl. Funnies requiring manual post-processing: * accel/tcg/cputlb.c trace points are in trace-events. * block.c and blockdev.c trace points are in block/trace-events. * hw/block/nvme.c uses the preprocessor to hide its trace point use from cleanup-trace-events.pl. * hw/tpm/tpm_spapr.c uses pseudo trace point tpm_spapr_show_buffer to guard debug code. * include/hw/xen/xen_common.h trace points are in hw/xen/trace-events. * linux-user/trace-events abbreviates a tedious list of filenames to */signal.c. * net/colo-compare and net/filter-rewriter.c use pseudo trace points colo_compare_miscompare and colo_filter_rewriter_debug to guard debug code. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200806141334.3646302-5-armbru@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2020-09-09Use DECLARE_*CHECKER* macrosEduardo Habkost
Generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]') Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-12-ehabkost@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-13-ehabkost@redhat.com> Message-Id: <20200831210740.126168-14-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-09Move QOM typedefs and add missing includesEduardo Habkost
Some typedefs and macros are defined after the type check macros. This makes it difficult to automatically replace their definitions with OBJECT_DECLARE_TYPE. Patch generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]') which will split "typdef struct { ... } TypedefName" declarations. Followed by: $ ./scripts/codeconverter/converter.py -i --pattern=MoveSymbols \ $(git grep -l '' -- '*.[ch]') which will: - move the typedefs and #defines above the type check macros - add missing #include "qom/object.h" lines if necessary Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-9-ehabkost@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-10-ehabkost@redhat.com> Message-Id: <20200831210740.126168-11-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-09hw/mips/fuloong2e: Convert pointless error message to an assert()Philippe Mathieu-Daudé
Displaying "vt82c686b_init error" doesn't give any hint about why this call failed. As this message targets developers and not users, replace the pointless error message by a call to assert() which will provide more useful information. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Huacai Chen <chenhc@lemote.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200901104043.91383-3-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-08Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.2-20200908' ↵Peter Maydell
into staging ppc patch queue 2020-09-08 This supersedes ppc-for-5.2-20200904, it fixes a couple of bugs in that PR and adds a few extra patches. Next pull request for qemu-5.2. The biggest thing here is the generalization of ARM's start-powered-off machine property to all targets. This can fix a number of odd little edge cases where KVM could run vcpus before they were properly initialized. This does include changes to a number of files that aren't normally in my purview. There are suitable Acked-by lines and Peter requested this come in via my tree, since the most pressing requirement for it is in pseries machines with the POWER secure virtual machine facility. In addition we have: * Daniel Barboza's rework and clean up of pseries machine NUMA handling * Correction to behaviour of the nvdimm= generic machine property on pseries * An optimization to the allocation of XIVE interrupts on KVM * Some fixes for confused behaviour with kernel_irqchip when both XICS and XIVE are in play * Add HIOMAP comamnd to pnv flash * Properly advertise the fact that spapr_vscsi doesn't handle hotplugged disks * Some assorted minor enhancements # gpg: Signature made Tue 08 Sep 2020 06:19:34 BST # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-5.2-20200908: (33 commits) spapr_numa: use spapr_numa_get_vcpu_assoc() in home_node hcall spapr_numa: create a vcpu associativity helper spapr: move h_home_node_associativity to spapr_numa.c spapr_numa: move NVLink2 associativity handling to spapr_numa.c spapr, spapr_numa: move lookup-arrays handling to spapr_numa.c spapr, spapr_numa: handle vcpu ibm,associativity spapr: introduce SpaprMachineState::numa_assoc_array ppc/spapr_nvdimm: turn spapr_dt_nvdimm() static ppc: introducing spapr_numa.c NUMA code helper hw/ppc/ppc4xx_pci: Replace pointless warning by assert() hw/ppc/ppc4xx_pci: Use ARRAY_SIZE() instead of magic value target/s390x: Use start-powered-off CPUState property sparc/sun4m: Use start-powered-off CPUState property sparc/sun4m: Don't set cs->halted = 0 in main_cpu_reset() mips/cps: Use start-powered-off CPUState property ppc/e500: Use start-powered-off CPUState property ppc/spapr: Use start-powered-off CPUState property target/arm: Move setting of CPU halted state to generic code target/arm: Move start-powered-off property to generic CPUState ppc/spapr_nvdimm: do not enable support with 'nvdimm=off' ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-17 05:18:09 +0000