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AgeCommit message (Expand)Author
2018-12-21spapr: add a 'reset' method to the sPAPR IRQ backendCédric Le Goater
2018-12-21spapr: allocate the interrupt thread context under the CPU coreCédric Le Goater
2018-12-21spapr: add device tree support for the XIVE exploitation modeCédric Le Goater
2018-12-21spapr: add hcalls support for the XIVE exploitation interrupt modeCédric Le Goater
2018-12-21spapr/xive: use the VCPU id as a NVT identifierCédric Le Goater
2018-12-21spapr/xive: introduce a XIVE interrupt controllerCédric Le Goater
2018-12-21ppc/xive: notify the CPU when the interrupt priority is more privilegedCédric Le Goater
2018-12-21ppc/xive: introduce a simplified XIVE presenterCédric Le Goater
2018-12-21ppc/xive: introduce the XIVE interrupt thread contextCédric Le Goater
2018-12-21ppc/xive: add support for the END Event State BuffersCédric Le Goater
2018-12-21ppc/xive: introduce the XIVE Event Notification DescriptorsCédric Le Goater
2018-12-21ppc/xive: introduce the XiveRouter modelCédric Le Goater
2018-12-21ppc/xive: introduce the XiveNotifier interfaceCédric Le Goater
2018-12-21ppc/xive: add support for the LSI interrupt sourcesCédric Le Goater
2018-12-21ppc/xive: introduce a XIVE interrupt source modelCédric Le Goater
2018-12-16Merge remote-tracking branch 'remotes/pmaydell/tags/pull-misc-20181214' into ...Peter Maydell
2018-12-14Rename cpu_physical_memory_write_rom() to address_space_write_rom()Peter Maydell
2018-12-13target/arm: Introduce arm_hcr_el2_effRichard Henderson
2018-12-13intc/puv3_intc: Convert sysbus init function to realize functionMao Zhongyi
2018-11-27vmstate: constify VMStateFieldMarc-André Lureau
2018-10-24target/arm: Move some system registers into a substructureRichard Henderson
2018-10-19ioapic: Fix error handling in realize()Markus Armbruster
2018-10-19Use error_fatal to simplify obvious fatal errors (again)Markus Armbruster
2018-10-19error: Fix use of error_prepend() with &error_fatal, &error_abortMarkus Armbruster
2018-09-25hw/intc/arm_gic: Drop GIC_BASE_IRQ macroPeter Maydell
2018-08-24hw/intc/arm_gic: Make per-cpu GICH memory regions 0x200 bytes largePeter Maydell
2018-08-23hw/intc/apic: Switch away from old_mmioPeter Maydell
2018-08-20nvic: Expose NMI linePeter Maydell
2018-08-20hw/intc/arm_gicv3_its: downgrade error_report to warn_report in kvm_arm_its_r...Jia He
2018-08-14target/arm: Provide accessor functions for HCR_EL2.{IMO, FMO, AMO}Peter Maydell
2018-08-14intc/arm_gic: Improve tracesLuc Michel
2018-08-14intc/arm_gic: Implement maintenance interrupt generationLuc Michel
2018-08-14intc/arm_gic: Implement gic_update_virt() functionLuc Michel
2018-08-14intc/arm_gic: Implement the virtual interface registersLuc Michel
2018-08-14intc/arm_gic: Wire the vCPU interfaceLuc Michel
2018-08-14intc/arm_gic: Implement virtualization extensions in gic_cpu_(read|write)Luc Michel
2018-08-14intc/arm_gic: Implement virtualization extensions in gic_(deactivate|complete...Luc Michel
2018-08-14intc/arm_gic: Implement virtualization extensions in gic_acknowledge_irqLuc Michel
2018-08-14intc/arm_gic: Implement virtualization extensions in gic_(activate_irq|drop_p...Luc Michel
2018-08-14intc/arm_gic: Add virtualization enabled IRQ helper functionsLuc Michel
2018-08-14intc/arm_gic: Refactor secure/ns access check in the CPU interfaceLuc Michel
2018-08-14intc/arm_gic: Add virtualization extensions helper macros and functionsLuc Michel
2018-08-14intc/arm_gic: Add virtual interface register definitionsLuc Michel
2018-08-14intc/arm_gic: Add the virtualization extensions to the GIC stateLuc Michel
2018-08-14intc/arm_gic: Remove some dead code and put some functions staticLuc Michel
2018-08-14intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registersLuc Michel
2018-08-14intc/arm_gic: Refactor operations on the distributorLuc Michel
2018-08-14nvic: Change NVIC to support ARMv6-MJulia Suvorova
2018-08-14arm: Add ARMv6-M programmer's model supportJulia Suvorova
2018-08-14nvic: Handle ARMv6-M SCS reserved registersJulia Suvorova
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