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2018-02-09s390x/tcg: cache the qemu flic in a central functionDavid Hildenbrand
This avoids tons of conversions when handling interrupts. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-17-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/flic: optimize CPU wakeup for TCGDavid Hildenbrand
Kicking all CPUs on every floating interrupt is far from efficient. Let's optimize it at least a little bit. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-12-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/flic: implement qemu_s390_clear_io_flic()David Hildenbrand
Now that we have access to the io interrupts, we can implement clear_io_irq() for TCG. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-11-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/flic: make floating interrupts on TCG actually floatingDavid Hildenbrand
Move floating interrupt handling into the flic. Floating interrupts will now be considered by all CPUs, not just CPU #0. While at it, convert I/O interrupts to use a list and make sure we properly consider I/O sub-classes in s390_cpu_has_io_int(). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-9-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/flic: no need to call s390_io_interrupt() from flicDavid Hildenbrand
We can directly call the right function. Suggested-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/flic: factor out injection of floating interruptsDavid Hildenbrand
Let the flic device handle it internally. This will allow us to later on store floating interrupts in the flic for the TCG case. This now also simplifies kvm.c. All that's left is the fallback interface for floating interrupts, which is now triggered directly via the flic in case anything goes wrong. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/tcg: simplify lookup of flicDavid Hildenbrand
We can simply search for an object of our common type. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-4-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/flic: simplify flic initializationDavid Hildenbrand
This makes it clearer, which device is used for which accelerator. Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-3-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-05qdev: use device_class_set_parent_realize/unrealize/reset()Philippe Mathieu-Daudé
changes generated using the following Coccinelle patch: @@ type DeviceParentClass; DeviceParentClass *pc; DeviceClass *dc; identifier parent_fn; identifier child_fn; @@ ( +device_class_set_parent_realize(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->realize; ... -dc->realize = child_fn; | +device_class_set_parent_unrealize(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->unrealize; ... -dc->unrealize = child_fn; | +device_class_set_parent_reset(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->reset; ... -dc->reset = child_fn; ) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180114020412.26160-4-f4bug@amsat.org> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-01-26xlnx-zynqmp-ipi: Initial version of the Xilinx IPI deviceAlistair Francis
This is the initial version of the Inter Processor Interrupt device. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-26xlnx-pmu-iomod-intc: Add the PMU Interrupt controllerAlistair Francis
Add the PMU IO Module Interrupt controller device. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-01-25Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20180125' into staging target-arm queue: * target/arm: Fix address truncation in 64-bit pagetable walks * i.MX: Fix FEC/ENET receive functions * target/arm: preparatory refactoring for SVE emulation * hw/intc/arm_gic: Prevent the GIC from signaling an IRQ when it's "active and pending" * hw/intc/arm_gic: Fix C_RPR value on idle priority * hw/intc/arm_gic: Fix group priority computation for group 1 IRQs * hw/intc/arm_gic: Fix the NS view of C_BPR when C_CTRL.CBPR is 1 * hw/arm/virt: Check that the CPU realize method succeeded * sdhci: fix a NULL pointer dereference due to uninitialized AddressSpace object * xilinx_spips: Correct usage of an uninitialized local variable * pl110: Implement vertical compare/next base interrupts # gpg: Signature made Thu 25 Jan 2018 12:59:25 GMT # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180125: (21 commits) pl110: Implement vertical compare/next base interrupts xilinx_spips: Correct usage of an uninitialized local variable sdhci: fix a NULL pointer dereference due to uninitialized AddresSpace object hw/arm/virt: Check that the CPU realize method succeeded hw/intc/arm_gic: Fix the NS view of C_BPR when C_CTRL.CBPR is 1 hw/intc/arm_gic: Fix group priority computation for group 1 IRQs hw/intc/arm_gic: Fix C_RPR value on idle priority hw/intc/arm_gic: Prevent the GIC from signaling an IRQ when it's "active and pending" target/arm: Simplify fp_exception_el for user-only target/arm: Hoist store to flags output in cpu_get_tb_cpu_state target/arm: Move cpu_get_tb_cpu_state out of line target/arm: Add ARM_FEATURE_SVE vmstate: Add VMSTATE_UINT64_SUB_ARRAY target/arm: Add aa{32, 64}_vfp_{dreg, qreg} helpers target/arm: Change the type of vfp.regs target/arm: Use pointers in neon tbl helper target/arm: Use pointers in neon zip/uzp helpers target/arm: Use pointers in crypto helpers target/arm: Mark disas_set_insn_syndrome inline i.MX: Fix FEC/ENET receive funtions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-01-25hw/intc/arm_gic: Fix the NS view of C_BPR when C_CTRL.CBPR is 1Luc MICHEL
When C_CTRL.CBPR is 1, the Non-Secure view of C_BPR is altered: - A Non-Secure read of C_BPR should return the BPR value plus 1, saturated to 7, - A Non-Secure write should be ignored. Signed-off-by: Luc MICHEL <luc.michel@git.antfield.fr> Message-id: 20180119145756.7629-6-luc.michel@greensocs.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fixed comment typo] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-01-25hw/intc/arm_gic: Fix group priority computation for group 1 IRQsLuc MICHEL
When determining the group priority of a group 1 IRQ, if C_CTRL.CBPR is 0, the non-secure BPR value is used. However, this value must be incremented by one so that it matches the secure world number of implemented priority bits (NS world has one less priority bit compared to the Secure world). Signed-off-by: Luc MICHEL <luc.michel@git.antfield.fr> Message-id: 20180119145756.7629-5-luc.michel@greensocs.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: add assert, as the gicv3 code has] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-01-25hw/intc/arm_gic: Fix C_RPR value on idle priorityLuc MICHEL
When there is no active interrupts in the GIC, a read to the C_RPR register should return the value of the "Idle priority", which is either the maximum value an IRQ priority field can be set to, or 0xff. Since the QEMU GIC model implements all the 8 priority bits, the Idle priority is 0xff. Internally, when there is no active interrupt, the running priority value is 0x100. The gic_get_running_priority function returns an uint8_t and thus, truncate this value to 0x00 when returning it. This is wrong since a value of 0x00 correspond to the maximum possible priority. This commit fixes the returned value when the internal value is 0x100. Note that it is correct for the Non-Secure view to return 0xff even though from the NS world point of view, only 7 priority bits are implemented. The specification states that the Idle priority can be 0xff even when not all the 8 priority bits are implemented. This has been verified against a real GICv2 hardware on a Xilinx ZynqMP based board. Regarding the ARM11MPCore version of the GIC, the specification is not clear on that point, so this commit does not alter its behavior. Signed-off-by: Luc MICHEL <luc.michel@git.antfield.fr> Message-id: 20180119145756.7629-4-luc.michel@greensocs.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-01-25hw/intc/arm_gic: Prevent the GIC from signaling an IRQ when it's "active and ↵Luc MICHEL
pending" In the GIC, when an IRQ is acknowledged, its state goes from "pending" to: - "active" if the corresponding IRQ pin has been de-asserted - "active and pending" otherwise. The GICv2 manual states that when a IRQ becomes active (or active and pending), the GIC should either signal another (higher priority) IRQ to the CPU if there is one, or de-assert the CPU IRQ pin. The current implementation of the GIC in QEMU does not check if the IRQ is already active when looking for pending interrupts with sufficient priority in gic_update(). This can lead to signaling an interrupt that is already active. This usually happens when splitting priority drop and interrupt deactivation. On priority drop, the IRQ stays active until deactivation. If it becomes pending again, chances are that it will be incorrectly selected as best_irq in gic_update(). This commit fixes this by checking if the IRQ is not already active when looking for best_irq in gic_update(). Note that regarding the ARM11MPCore GIC version, the corresponding manual is not clear on that point, but it has has no priority drop/interrupt deactivation separation, so this case should not happen. Signed-off-by: Luc MICHEL <luc.michel@git.antfield.fr> Message-id: 20180119145756.7629-3-luc.michel@greensocs.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-01-24sparc/leon3 irqmp: fix IRQ software ackJean-Christophe Dubois
With the LEON3 IRQ controller IRQs can be acknowledged 2 ways: * Explicitly by software writing to the CLEAR_OFFSET register * Implicitly when the procesor is done running the trap handler attached to the IRQ. The actual IRQMP code only allows the implicit processor triggered IRQ ack. If software write explicitly to the CLEAR_OFFSET register, this will clear the pending bit in the register value but this will not lower the ongoing raised IRQ with the processor. The IRQ will be kept raised to the LEON processor until the related trap handler is run and the processor implicitly ack the interrupt. So with the actual IRQMP code trap handler have to be run even if the software has already done its job by clearing the pending bit. This feature has been tested on another LEON3 simulator (tsim_leon3 from Gaisler) and it turns out that the Qemu implementation is not equivalent to the tsim one. In tsim, if software does clear a pending interrupt before the related interrupt handler is triggered the said interrupt handler will not be called. This patch brings the Qemu IRQMP implementation in line with the tsim implementation by allowing IRQ to be acknowledged by software only. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2018-01-22Replace all occurances of __FUNCTION__ with __func__Alistair Francis
Replace all occurs of __FUNCTION__ except for the check in checkpatch with the non GCC specific __func__. One line in hcd-musb.c was manually tweaked to pass checkpatch. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> [THH: Removed hunks related to pxa2xx_mmci.c (fixed already)] Signed-off-by: Thomas Huth <thuth@redhat.com>
2018-01-16hw/intc/armv7m: Support byte and halfword accesses to CFSRPeter Maydell
The Configurable Fault Status Register for ARMv7M and v8M is supposed to be byte and halfword accessible, but we were only implementing word accesses. Add support for the other access sizes, which are used by the Zephyr RTOS. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reported-by: Andy Gross <andy.gross@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1512742372-31517-1-git-send-email-peter.maydell@linaro.org
2018-01-11hw/intc/arm_gic: reserved register addresses are RAZ/WIPeter Maydell
The GICv2 specification says that reserved register addresses must RAZ/WI; now that we implement external abort handling for Arm CPUs this means we must return MEMTX_OK rather than MEMTX_ERROR, to avoid generating a spurious guest data abort. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1513183941-24300-3-git-send-email-peter.maydell@linaro.org Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
2018-01-11hw/intc/arm_gicv3: Make reserved register addresses RAZ/WIPeter Maydell
The GICv3 specification says that reserved register addresses should RAZ/WI. This means we need to return MEMTX_OK, not MEMTX_ERROR, because now that we support generating external aborts the latter will cause an abort on new board models. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1513183941-24300-2-git-send-email-peter.maydell@linaro.org Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
2018-01-09sun4m: remove include/hw/sparc/sun4m.h and all references to itMark Cave-Ayland
With the previous commit there is now nothing left in sun4m.h so it can be removed, along with all remaining references to it. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-12-22apic: add function to apic that will be used by hvfSergio Andres Gomez Del Real
This patch adds the function apic_get_highest_priority_irr to apic.c and exports it through the interface in apic.h for use by hvf. Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com> Message-Id: <20170913090522.4022-8-Sergio.G.DelReal@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-21i8259: move TYPE_INTERRUPT_STATS_PROVIDER upperPeter Xu
Now both classes (i8259, i8259-kvm) support this. Move this upper to the common class code. Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20171210063819.14892-6-peterx@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-21kvm-i8259: support "info pic" and "info irq"Peter Xu
Let's leverage the i8259 common code for kvm-i8259 too. I think it's still possible that stats can lost when i8259 is in kernel and meanwhile when irqfd is used, e.g., by vfio or vhost devices. However that should be rare IMHO since they should be using MSIs mostly if they really want performance (that's why people use vhost and device assignment), and no old INTx should be used. As long as the INTx users are emulated in QEMU the stats will be correct. For "info pic", it should be always accurate since we fetch kvm regs before dump. More importantly, it's just too simple to do this now - it's only 10+ LOC to gain this feature. Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20171210063819.14892-5-peterx@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-21i8259: generalize statistics into common codePeter Xu
It was only for userspace i8259. Move it to general code so that kvm-i8259 can also use it in the future. Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20171210063819.14892-4-peterx@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-21i8259: use DEBUG_IRQ_COUNT alwaysPeter Xu
It's not really scary to even enable it forever. After all it's i8259, and it's even not the kernel one. Then we can remove quite a few of lines to make it cleaner. And "info irq" will always work for it. Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20171210063819.14892-3-peterx@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-21i8259: convert DPRINTFs into tracePeter Xu
One thing to mention is that in pic_set_irq() I need to uncomment a few lines in the macros to make sure IRQ value calculation is correct. Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20171210063819.14892-2-peterx@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-18misc: drop old i386 dependencyPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-12-15spapr: introduce a spapr_qirq() helperCédric Le Goater
xics_get_qirq() is only used by the sPAPR machine. Let's move it there and change its name to reflect its scope. It will be useful for XIVE support which will use its own set of qirqs. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-12-15spapr: move the IRQ allocation routines under the machineCédric Le Goater
Also change the prototype to use a sPAPRMachineState and prefix them with spapr_irq_. It will let us synchronise the IRQ allocation with the XIVE interrupt mode when available. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-12-15ppc/xics: assign of the CPU 'intc' pointer under the coreCédric Le Goater
The 'intc' pointer of the CPU references the interrupt presenter in the XICS interrupt mode. When the XIVE interrupt mode is available and activated, the machine will need to reassign this pointer to reflect the change. Moving this assignment under the realize routine of the CPU will ease the process when the interrupt mode is toggled. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-12-15ppc/xics: introduce an icp_create() helperCédric Le Goater
The sPAPR and the PowerNV core objects create the interrupt presenter object of the CPUs in a very similar way. Let's provide a common routine in which we use the presenter 'type' as a child identifier. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-12-15openpic: debug w/ info_report()Michael Davidsaver
Replace *printf() with *_report(). Remove trailing new lines. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-12-15ppc/xics: remove useless if conditionCédric Le Goater
The previous code section uses a 'first < 0' test and returns. Therefore, there is no need to test the 'first' variable against '>= 0' afterwards. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-12-13nvic: Make systick bankedPeter Maydell
For the v8M security extension, there should be two systick devices, which use separate banked systick exceptions. The register interface is banked in the same way as for other banked registers, including the existence of an NS alias region for secure code to access the nonsecure timer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1512154296-5652-3-git-send-email-peter.maydell@linaro.org
2017-12-13nvic: Make nvic_sysreg_ns_ops work with any MemoryRegionPeter Maydell
Generalize nvic_sysreg_ns_ops so that we can pass it an arbitrary MemoryRegion which it will use as the underlying register implementation to apply the NS-alias behaviour to. We'll want this so we can do the same with systick. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1512154296-5652-2-git-send-email-peter.maydell@linaro.org
2017-12-13hw/intc/arm_gicv3_its: Implement full resetEric Auger
Voiding the ITS caches is not supposed to happen via individual register writes. So we introduced a dedicated ITS KVM device ioctl to perform a cold reset of the ITS: KVM_DEV_ARM_VGIC_GRP_CTRL/KVM_DEV_ARM_ITS_CTRL_RESET. Let's use this latter if the kernel supports it. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1511883692-11511-5-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-12-13hw/intc/arm_gicv3_its: Implement a minimalist resetEric Auger
At the moment the ITS is not properly reset and this causes various bugs on save/restore. We implement a minimalist reset through individual register writes but for kernel versions before v4.15 this fails voiding the vITS cache. We cannot claim we have a comprehensive reset (hence the error message) but that's better than nothing. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1511883692-11511-3-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-12-13hw/intc/arm_gicv3_its: Don't call post_load on resetEric Auger
From the very beginning, post_load() was called from common reset. This is not standard and obliged to discriminate the reset case from the restore case using the iidr value. Let's get rid of that call. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1511883692-11511-2-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-11-20nvic: Fix ARMv7M MPU_RBAR readsPeter Maydell
Fix an incorrect mask expression in the handling of v7M MPU_RBAR reads that meant that we would always report the ADDR field as zero. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1509732813-22957-1-git-send-email-peter.maydell@linaro.org
2017-11-16Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
Miscellaneous bugfixes # gpg: Signature made Wed 15 Nov 2017 15:27:25 GMT # gpg: using RSA key 0xBFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: fix scripts/update-linux-headers.sh here document exec: Do not resolve subpage in mru_section util/stats64: Fix min/max comparisons cpu-exec: avoid cpu_exec_nocache infinite loop with record/replay cpu-exec: don't overwrite exception_index vhost-user-scsi: add missing virtqueue_size param target-i386: adds PV_TLB_FLUSH CPUID feature bit thread-posix: fix qemu_rec_mutex_trylock macro Makefile: simpler/faster "make help" ioapic/tracing: Remove last DPRINTFs Enable 8-byte wide MMIO for 16550 serial devices Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-11-14ioapic/tracing: Remove last DPRINTFsDr. David Alan Gilbert
Remove the last few DPRINTFs from hw/intc/ioapic.c and turn them into tracing. In one case it's a new trace, in the others it's just adding a parameter to the existing traces. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20171102180310.24760-1-dgilbert@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-11-14xics/kvm: synchonize state before 'info pic'Greg Kurz
When using the emulated XICS, the 'info pic' monitor command shows: CPU 0 XIRR=ff000000 ((nil)) PP=ff MFRR=ff ICS 1000..13ff 0x10040060340 1000 MSI 05 00 1001 MSI 05 00 1002 MSI 05 00 1003 MSI ff 00 1004 LSI ff 00 1005 LSI ff 00 1006 LSI ff 00 1007 LSI ff 00 1008 MSI 05 00 1009 MSI 05 00 100a MSI 05 00 100b MSI 05 00 100c MSI 05 00 but when using the in-kernel XICS with the very same guest, we get: CPU 0 XIRR=00000000 ((nil)) PP=ff MFRR=ff ICS 1000..13ff 0x10032e00340 1000 MSI ff 00 1001 MSI ff 00 1002 MSI ff 00 1003 MSI ff 00 1004 LSI ff 00 1005 LSI ff 00 1006 LSI ff 00 1007 LSI ff 00 1008 MSI ff 00 1009 MSI ff 00 100a MSI ff 00 100b MSI ff 00 100c MSI ff 00 ie, all irqs are masked and XIRR is null, while we should get the same output as with the emulated XICS. If the guest is then migrated, 'info pic' shows the expected values on both source and destination. The problem is that QEMU doesn't synchronize with KVM before printing the XICS state. Migration happens to fix the output because it enforces synchronization with KVM. To fix the invalid output of 'info pic', this patch introduces a new synchronize_state operation for both ICPStateClass and ICSStateClass. The ICP operation relies on run_on_cpu() in order to kick the vCPU and avoid sleeping on KVM_GET_ONE_REG. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-11-07hw/intc/arm_gicv3_its: Don't abort on table save failureEric Auger
The ITS is not fully properly reset at the moment. Caches are not emptied. After a reset, in case we attempt to save the state before the bound devices have registered their MSIs and after the 1st level table has been allocated by the ITS driver (device BASER is valid), the first level entries are still invalid. If the device cache is not empty (devices registered before the reset), vgic_its_save_device_tables fails with -EINVAL. This causes a QEMU abort(). Cc: qemu-stable@nongnu.org Signed-off-by: Eric Auger <eric.auger@redhat.com> Reported-by: wanghaibin <wanghaibin.wang@huawei.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-11-07hw/intc/arm_gicv3_its: Fix the VM termination in vm_change_state_handler()Shanker Donthineni
The commit cddafd8f353d ("hw/intc/arm_gicv3_its: Implement state save /restore") breaks the backward compatibility with the older kernels where vITS save/restore support is not available. The vmstate function vm_change_state_handler() should not be registered if the running kernel doesn't support ITS save/restore feature. Otherwise VM instance will be killed whenever vmstate callback function is invoked. Observed a virtual machine shutdown with QEMU-2.10+linux-4.11 when testing the reboot command "virsh reboot <domain> --mode acpi" instead of reboot. KVM Error: 'KVM_SET_DEVICE_ATTR failed: Group 4 attr 0x00000000000001' Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 1509712671-16299-1-git-send-email-shankerd@codeaurora.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-21openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC)Stafford Horne
Add OpenRISC Multicore PIC which handles inter processor interrupts (IPI) between cores. In OpenRISC all device interrupts are routed to each core enabling this device to be simple. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2017-10-12nvic: Fix miscalculation of offsets into ITNS arrayPeter Maydell
This calculation of the first exception vector in the ITNS<n> register being accessed: int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ; is incorrect, because offset is in bytes, so we only want to multiply by 8. Spotted by Coverity (CID 1381484, CID 1381488), though it is not correct that it actually overflows the buffer, because we have a 'startvec + i < s->num_irq' guard. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1507650856-11718-1-git-send-email-peter.maydell@linaro.org
2017-10-12nvic: Add missing 'break'Peter Maydell
Coverity points out that we forgot the 'break' for the SAU_CTRL write case (CID1381683). This has no actual visible consequences because it happens that the following case is effectively a no-op. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1507742676-9908-1-git-send-email-peter.maydell@linaro.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-06nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bitPeter Maydell
When we added support for the new SHCSR bits in v8M in commit 437d59c17e9 the code to support writing to the new HARDFAULTPENDED bit was accidentally only added for non-secure writes; the secure banked version of the bit should also be writable. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1506092407-26985-21-git-send-email-peter.maydell@linaro.org
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