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AgeCommit message (Expand)Author
2023-02-03target/arm: Mark up sysregs for HFGRTR bits 36..63Peter Maydell
2023-02-03hvf: arm: Add support for GICv3Alexander Graf
2023-01-20Merge tag 'pull-include-2023-01-20' of https://repo.or.cz/qemu/armbru into st...Peter Maydell
2023-01-20include/hw/ppc: Split pnv_chip.h off pnv.hMarkus Armbruster
2023-01-19Merge tag 'trivial-branch-for-8.0-pull-request' of https://gitlab.com/laurent...Peter Maydell
2023-01-18bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plxPhilippe Mathieu-Daudé
2023-01-16hw/intc: Mark more interrupt-controller files as target independentThomas Huth
2023-01-16hw/intc: Move some files out of the target-specific source setPhilippe Mathieu-Daudé
2023-01-16Merge tag 'mips-20230113' of https://github.com/philmd/qemu into stagingPeter Maydell
2023-01-13hw/intc: Extract the IRQ counting functions into a separate fileThomas Huth
2023-01-13hw/intc/i8259: Make using the isa_pic singleton more type-safeBernhard Beschow
2023-01-12hw/intc/xilinx_intc: Use 'XpsIntc' typedef instead of 'struct xlx_pic'Philippe Mathieu-Daudé
2023-01-12hw/intc/omap_intc: Use CamelCase for TYPE_OMAP_INTC type namePhilippe Mathieu-Daudé
2023-01-12hw/arm/omap: Drop useless casts from void * to pointerPhilippe Mathieu-Daudé
2023-01-07Merge tag 'pull-loongarch-20230106' of https://gitlab.com/gaosong/qemu into s...Peter Maydell
2023-01-06hw/intc/loongarch_pch: Change default irq number of pch irq controllerTianrui Zhao
2023-01-06hw/intc/loongarch_pch_pic: add irq number propertyTianrui Zhao
2023-01-06hw/intc/loongarch_pch_msi: add irq number propertyTianrui Zhao
2023-01-06hw/intc: sifive_plic: Fix the pending register range checkBin Meng
2023-01-06hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0Bin Meng
2023-01-06hw/intc: sifive_plic: Update "num-sources" property default valueBin Meng
2023-01-06hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in ...Bin Meng
2023-01-06hw/intc: sifive_plic: Improve robustness of the PLIC config parserBin Meng
2023-01-06hw/intc: sifive_plic: Drop PLICMode_HBin Meng
2023-01-06hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllersBin Meng
2023-01-06hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLICBin Meng
2023-01-06hw/intc: sifive_plic: fix out-of-bound access of source_priority arrayJim Shu
2023-01-06hw/intc: sifive_plic: Renumber the S irqs for numa supportFrédéric Pétrot
2022-12-16hw/intc/xics: Convert TYPE_ICS to 3-phase resetPeter Maydell
2022-12-16hw/intc/xics: Reset TYPE_ICS objects with device_cold_reset()Peter Maydell
2022-12-15hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase resetPeter Maydell
2022-12-15hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase resetPeter Maydell
2022-12-15hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase resetPeter Maydell
2022-12-15hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase resetPeter Maydell
2022-12-15hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase resetPeter Maydell
2022-12-15hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase resetPeter Maydell
2022-12-15hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase resetPeter Maydell
2022-12-15hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisementLuke Starrett
2022-11-21hw/intc: add implementation of GICD_IIDR to Arm GICAlex Bennée
2022-11-21hw/intc: clean-up access to GIC multi-byte registersAlex Bennée
2022-11-14hw/intc/arm_gicv3: fix prio masking on pmr writeJens Wiklander
2022-11-04hw/intc: Fix LoongArch extioi coreisr accessingXiaojuan Yang
2022-11-04hw/intc: Convert the memops to with_attrs in LoongArch extioiXiaojuan Yang
2022-10-31hw/ppc/mac.h: Rename to include/hw/nvram/mac_nvram.hBALATON Zoltan
2022-10-17hw/intc: Fix LoongArch ipi device emulationXiaojuan Yang
2022-10-14hw/intc: sifive_plic: change interrupt priority register to WARL fieldJim Shu
2022-10-14hw/intc: sifive_plic: fix hard-coded max priority levelJim Shu
2022-09-22hw/intc/xics: Avoid dynamic stack allocationPhilippe Mathieu-Daudé
2022-09-07hw/intc: Move mtimer/mtimecmp to aclintAtish Patra
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel
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