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AgeCommit message (Expand)Author
2022-09-22hw/intc/xics: Avoid dynamic stack allocationPhilippe Mathieu-Daudé
2022-09-07hw/intc: Move mtimer/mtimecmp to aclintAtish Patra
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel
2022-08-31hw/intc/ppc-uic: Convert ppc-uic to a PPC4xx DCR deviceBALATON Zoltan
2022-08-01misc: fix commonly doubled up wordsDaniel P. Berrangé
2022-07-28hw/intc: sifive_plic: Fix multi-socket plic configuraitonAtish Patra
2022-07-19hw/intc/loongarch_pch_pic: Fix bugs for update_irq functionXiaojuan Yang
2022-07-18ppc64: Allocate IRQ lines with qdev_init_gpio_in()Cédric Le Goater
2022-07-18hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held highPeter Maydell
2022-07-06ppc: Define SETFIELD for the ppc targetAlexey Kardashevskiy
2022-07-05hw/intc/loongarch_ipi: Fix mail send and any send functionXiaojuan Yang
2022-07-05hw/intc/loongarch_ipi: Fix ipi device access of 64bitsXiaojuan Yang
2022-07-04hw/intc/loongarch_pch_msi: Fix msi vector convertionMao Bibo
2022-06-28Trivial: 3 char repeat typosDr. David Alan Gilbert
2022-06-20pnv/xive2: Access direct mapped thread contexts from all chipsFrederic Barrat
2022-06-10hw/intc: sifive_plic: Avoid overflowing the addr_config bufferAlistair Francis
2022-06-08Fix 'writeable' typosPeter Maydell
2022-06-06hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)Xiaojuan Yang
2022-06-06hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)Xiaojuan Yang
2022-06-06hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)Xiaojuan Yang
2022-06-06hw/loongarch: Add LoongArch ipi interrupt support(IPI)Xiaojuan Yang
2022-05-26pnv/xive2: Don't overwrite PC registers when writing TCTXT registersFrederic Barrat
2022-05-24hw/intc: Pass correct hartid while updating mtimecmpAtish Patra
2022-05-19hw/intc/arm_gicv3: Provide ich_num_aprs()Peter Maydell
2022-05-19hw/intc/arm_gicv3: Use correct number of priority bits for the CPUPeter Maydell
2022-05-19hw/intc/arm_gicv3: Support configurable number of physical priority bitsPeter Maydell
2022-05-19hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constantPeter Maydell
2022-05-19hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1Peter Maydell
2022-05-19hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parametersPeter Maydell
2022-05-05ppc/xive: Update the state of the External interrupt signalFrederic Barrat
2022-05-05ppc/xive: Always recompute the PIPR when pushing an OS contextFrederic Barrat
2022-05-05target/arm: Replace sentinels with ARRAY_SIZE in cpregs.hRichard Henderson
2022-05-05target/arm: Split out cpregs.hRichard Henderson
2022-04-26hw/intc: Vectored Interrupt Controller (VIC)Amir Gonnen
2022-04-22Merge tag 'pull-target-arm-20220422-1' of https://git.linaro.org/people/pmayd...Richard Henderson
2022-04-22hw/intc/arm_gicv3: Allow 'revision' property to be set to 4Peter Maydell
2022-04-22hw/intc/arm_gicv3: Update ID and feature registers for GICv4Peter Maydell
2022-04-22hw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi()Peter Maydell
2022-04-22hw/intc/arm_gicv3_redist: Implement gicv3_redist_vinvall()Peter Maydell
2022-04-22hw/intc/arm_gicv3_redist: Implement gicv3_redist_mov_vlpi()Peter Maydell
2022-04-22hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov handlingPeter Maydell
2022-04-22hw/intc/arm_gicv3_redist: Implement gicv3_redist_vlpi_pending()Peter Maydell
2022-04-22hw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi()Peter Maydell
2022-04-22hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" codePeter Maydell
2022-04-22hw/intc/arm_gicv3_redist: Recalculate hppvlpi on VPENDBASER writesPeter Maydell
2022-04-22hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all LPIs" logicPeter Maydell
2022-04-22hw/intc/arm_gicv3_redist: Factor out "update hpplpi for one LPI" logicPeter Maydell
2022-04-22hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq unnecessarilyPeter Maydell
2022-04-22hw/intc/arm_gicv3_cpuif: Support vLPIsPeter Maydell
2022-04-22hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from gicv3_cpuif_virt_update()Peter Maydell
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