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AgeCommit message (Expand)Author
2023-09-11loongarch: mark loongarch_ipi_iocsr re-entrnacy safeAlexander Bulekov
2023-09-11apic: disable reentrancy detection for apic-msiAlexander Bulekov
2023-06-22hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1Peter Maydell
2023-05-18hw/intc/allwinner-a10-pic: Don't use set_bit()/clear_bit()Peter Maydell
2022-11-21hw/intc: add implementation of GICD_IIDR to Arm GICAlex Bennée
2022-11-21hw/intc: clean-up access to GIC multi-byte registersAlex Bennée
2022-11-14hw/intc/arm_gicv3: fix prio masking on pmr writeJens Wiklander
2022-11-04hw/intc: Fix LoongArch extioi coreisr accessingXiaojuan Yang
2022-11-04hw/intc: Convert the memops to with_attrs in LoongArch extioiXiaojuan Yang
2022-10-31hw/ppc/mac.h: Rename to include/hw/nvram/mac_nvram.hBALATON Zoltan
2022-10-17hw/intc: Fix LoongArch ipi device emulationXiaojuan Yang
2022-10-14hw/intc: sifive_plic: change interrupt priority register to WARL fieldJim Shu
2022-10-14hw/intc: sifive_plic: fix hard-coded max priority levelJim Shu
2022-09-22hw/intc/xics: Avoid dynamic stack allocationPhilippe Mathieu-Daudé
2022-09-07hw/intc: Move mtimer/mtimecmp to aclintAtish Patra
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel
2022-08-31hw/intc/ppc-uic: Convert ppc-uic to a PPC4xx DCR deviceBALATON Zoltan
2022-08-01misc: fix commonly doubled up wordsDaniel P. Berrangé
2022-07-28hw/intc: sifive_plic: Fix multi-socket plic configuraitonAtish Patra
2022-07-19hw/intc/loongarch_pch_pic: Fix bugs for update_irq functionXiaojuan Yang
2022-07-18ppc64: Allocate IRQ lines with qdev_init_gpio_in()Cédric Le Goater
2022-07-18hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held highPeter Maydell
2022-07-06ppc: Define SETFIELD for the ppc targetAlexey Kardashevskiy
2022-07-05hw/intc/loongarch_ipi: Fix mail send and any send functionXiaojuan Yang
2022-07-05hw/intc/loongarch_ipi: Fix ipi device access of 64bitsXiaojuan Yang
2022-07-04hw/intc/loongarch_pch_msi: Fix msi vector convertionMao Bibo
2022-06-28Trivial: 3 char repeat typosDr. David Alan Gilbert
2022-06-20pnv/xive2: Access direct mapped thread contexts from all chipsFrederic Barrat
2022-06-10hw/intc: sifive_plic: Avoid overflowing the addr_config bufferAlistair Francis
2022-06-08Fix 'writeable' typosPeter Maydell
2022-06-06hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)Xiaojuan Yang
2022-06-06hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)Xiaojuan Yang
2022-06-06hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)Xiaojuan Yang
2022-06-06hw/loongarch: Add LoongArch ipi interrupt support(IPI)Xiaojuan Yang
2022-05-26pnv/xive2: Don't overwrite PC registers when writing TCTXT registersFrederic Barrat
2022-05-24hw/intc: Pass correct hartid while updating mtimecmpAtish Patra
2022-05-19hw/intc/arm_gicv3: Provide ich_num_aprs()Peter Maydell
2022-05-19hw/intc/arm_gicv3: Use correct number of priority bits for the CPUPeter Maydell
2022-05-19hw/intc/arm_gicv3: Support configurable number of physical priority bitsPeter Maydell
2022-05-19hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constantPeter Maydell
2022-05-19hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1Peter Maydell
2022-05-19hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parametersPeter Maydell
2022-05-05ppc/xive: Update the state of the External interrupt signalFrederic Barrat
2022-05-05ppc/xive: Always recompute the PIPR when pushing an OS contextFrederic Barrat
2022-05-05target/arm: Replace sentinels with ARRAY_SIZE in cpregs.hRichard Henderson
2022-05-05target/arm: Split out cpregs.hRichard Henderson
2022-04-26hw/intc: Vectored Interrupt Controller (VIC)Amir Gonnen
2022-04-22Merge tag 'pull-target-arm-20220422-1' of https://git.linaro.org/people/pmayd...Richard Henderson
2022-04-22hw/intc/arm_gicv3: Allow 'revision' property to be set to 4Peter Maydell
2022-04-22hw/intc/arm_gicv3: Update ID and feature registers for GICv4Peter Maydell
generated by cgit v1.2.3 (git 2.26.2) at 2024-11-25 20:49:34 +0000